EVAL-ADM1026EB datasheet(14/56 Pages) AD

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ADM1026

Rev. A | Page 14 of 56

Bit 3 of EEPROM Register 3 is used for EEPROM write protec-

tion. Setting this bit prevents accidental programming or era-

sure of the EEPROM. If an EEPROM write or erase operation

is attempted when this bit is set, the ADM1026 responds with

No Acknowledge. This bit is write-once and can only be cleared

by a power-on reset.

EEPROM Register 3 Bit 7 is used for clock extend. Program-

ming an EEPROM byte takes approximately 250 µs, which

would limit the SMBus clock for repeated or block write opera-

tions. Because EEPROM block read/write access is slow, it is

recommended that this clock extend bit typically be set to 1.

This allows the ADM1026 to pull SCL low and extend the

clock pulse when it cannot accept any more data.

ADM1026 SMBus Operations

The SMBus specification defines several protocols for different

types of read and write operations. The ones used in the

ADM1026 are discussed below. The following abbreviations are

used in the diagrams:

Start

Write

Stop

Acknowledge

Read

No Acknowledge

ADM1026 Write Operations

Send Byte

In this operation, the master device sends a single command

byte to a slave device, as follows:

The master device asserts a start condition on the SDA.

The master sends the 7-bit slave address followed by the

write bit (low).

The addressed slave device asserts an ACK on the SDA.

The master sends a command code.

The slave asserts ACK on the SDA.

The master asserts a stop condition on the SDA and the

transaction ends.

In the ADM1026, the send byte protocol is used to write a

the same address or block read or write starting at that address.

This is illustrated in Figure 19.

SLAVE

ADDRESS

RAM

ADDRESS

(00h TO 6Fh)

Figure 19. Setting a RAM Address for Subsequent Read

If it is required to read data from the RAM immediately after

setting up the address, the master can assert a repeat start

condition immediately after the final ACK and carry out a

single byte read, block read, or block write operation without

asserting an intermediate stop condition.

Write Byte/Word

In this operation, the master device sends a command byte and

one or two data bytes to the slave device as follows:

The master device asserts a start condition on the SDA.

The master sends the 7-bit slave address followed by the

write bit (low).

The addressed slave device asserts an ACK on the SDA.

The master sends a command code.

The slave asserts an ACK on the SDA.

The master sends a data byte.

The slave asserts an ACK on the SDA.

The master sends a data byte (or may assert stop here.)

The slave asserts an ACK on the SDA.

10. The master asserts a stop condition on the SDA to end the

transaction.

In the ADM1026, the write byte/word protocol is used for four

purposes. The ADM1026 knows how to respond by the value of

the command byte and EEPROM Register 3.

The first purpose is to write a single byte of data to RAM. In

this case, the command byte is the RAM address from 00h to

6Fh and the (only) data byte is the actual data. This is illustrated

in Figure 20.

SLAVE

ADDRESS

RAM

ADDRESS

(00h TO 6Fh)

A DATA AP

Figure 20. Single Byte Write to RAM

The protocol is also used to set up a 2-byte EEPROM address

for a subsequent read or block read. In this case, the command

byte is the high byte of the EEPROM address from 80h to 9Fh.

The (only) data byte is the low byte of the EEPROM address.

This is illustrated in Figure 21.

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

Figure 21. Setting an EEPROM Address

If it is required to read data from the EEPROM immediately

after setting up the address, the master can assert a repeat start

condition immediately after the final ACK and carry out a

single-byte read or block read operation without asserting an

intermediate stop condition. In this case, Bit 0 of EEPROM

The third use is to erase a page of EEPROM memory. EEPROM

memory can be written to only if it is previously erased. Before

writing to one or more EEPROM memory locations that are

already programmed, the page or pages containing those

locations must first be erased. EEPROM memory is erased by

writing an EEPROM page address plus an arbitrary byte of data

with Bit 2 of EEPROM Register 3 set to 1.

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