EVAL-ADM1026EB datasheet(28/56 Pages) AD

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ADM1026

Rev. A | Page 28 of 56

ADM1026 Interrupt Structure

The Interrupt Structure of the ADM1026 is shown in Figure 53.

Interrupts can come from a number of sources, which are com-

bined to form a common INT output. When INT is asserted,

this output pulls low. The INT pin has an internal, 100 kΩ

pull-up resistor.

Analog/Temperature Inputs

As each analog measurement value is obtained and stored in the

appropriate value register, the value and the limits from the

corresponding limit registers are fed to the high and low limit

comparators. The device performs greater than comparisons to

the high limits. An out-of-limit is also generated if a result is

less than or equal to a low limit. The result of each comparison

(1 = out of limit, 0 = in limit) is routed to the corresponding

bit input of Interrupt Status Register 1, 2, or 4 via a data

demultiplexer, and used to set that bit high or low as appro-

priate. Status bits are self-clearing. If a bit in a status register is

set due to an out-of-limit measurement, it continues to cause

INT to be asserted as long as it remains set, as described later.

However, if a subsequent measurement is in limit, it is reset and

does not cause INT to be reasserted. Status bits are unaffected

by clearing the interrupt.

Interrupt Mask Registers 1, 2, and 4 have bits corresponding to

each of the interrupt status register bits. Setting an interrupt

mask bit high conceals an asserted status bit from display on

Interrupt Pin 17. Setting an interrupt mask bit low allows the

corresponding status bit to be asserted and displayed on Pin 17.

After mask gating, the status bits are all OR’ed together to

produce the analog and fan interrupt that is used to set a latch.

The output of this latch is OR’ed with other interrupt sources to

produce the INT output. This pulls low if any unmasked status

bit goes high, that is, when any measured value goes out of limit.

When an INT output caused by an out-of-limit analog/

temperature measurement is cleared by one of the methods

described later, the latch is reset. It is not set again, and INT is

not reasserted until after two local temperature measure-ments

have been taken, even if the status bit remains set or a new

analog/temperature event occurs, as shown in Figure 50. This

delay corresponds to almost two monitoring cycles, and is about

530 ms. However, interrupts from other sources such as a fan or

GPIO can still occur. This is illustrated in Figure 51.

START OF ANALOG

MONITORING

CYCLE

OUT-OF-LIMIT

MEASUREMENT

START OF ANALOG

MONITORING

CYCLE

INT

INT CLEARED

LOCAL

TEMPERATURE

MEASUREMENT

START OF ANALOG

MONITORING

CYCLE

INT RE-ASSERTED

OUT-OF-LIMIT

MEASUREMENT

FULL MONITORING CYCLE = 273ms

TEMPERATURE

LOCAL

MEASUREMENT

Figure 50. Delay After Clearing INT Before Reassertion

START OF ANALOG

MONITORING CYCLE

OUT-OF-LIMIT

MEASUREMENT

LOCAL TEMPEREATURE

MEASUREMENT

START OF ANALOG

MONITORING CYCLE

LOCAL TEMPERATURE

MEASUREMENT

START OF ANALOG

MONITORING CYCLE

INT

CLEARED

INT RE-ASSERTED

NEW INT

FROM FAN

NEW INT

FROM GPIO

GPIO DE-ASSERTED

INT

CLEARED

Figure 51. Other Interrupt Sources Can Reassert INT Immediately

EVAL-ADM1026EB Datasheet(PDF) 28 Page - Analog Devices

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