EVAL-ADM1026EB datasheet(12/56 Pages) AD

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ADM1026

Rev. A | Page 12 of 56

Serial Bus Interface

Control of the ADM1026 is carried out via the serial system

management bus (SMBus). The ADM1026 is connected to this

bus as a slave device, under the control of a master device.

The ADM1026 has a 7-bit serial bus slave address. When the

device is powered on, it does so with a default serial bus address.

The 5 MSBs of the address are set to 01011, and the 2 LSBs are

determined by the logical states of Pin 15 ADD/NTESTOUT.

This pin is a three-state input that can be grounded, connected

to VCC, or left open-circuit to give three different addresses.

Table 5. Address Pin Truth Table

ADD Pin

GND

No Connect

VCC

If ADD is left open-circuit, the default address is 0101110

(5Ch). ADD is sampled only at power-up on the first valid

SMBus transaction, so any changes made while the power is on

(and the address is locked) have no effect.

The facility to make hardwired changes to device addresses

allows the user to avoid conflicts with other devices sharing the

same serial bus, for example if more than one ADM1026 is used

in a system.

General SMBus Timing

Figure 17 and Figure 18 show timing diagrams for general read

and write operations using the SMBus. The SMBus specification

defines specific conditions for different types of read and write

operations, which are discussed later in this section.

The general SMBus protocol1 operates as follows:

The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line (SDA) while the serial clock line SCL remains

high. This indicates that a data stream follows. All slave

peripherals connected to the serial bus respond to the start

condition and shift in the next 8 bits, consisting of a 7-bit

slave address (MSB first) and an R/W bit, which determine

the direction of the data transfer, that is, whether data is

written to or read from the slave device

(0 = write, 1 = read).

The peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low during

the low period before the ninth clock pulse, known as the

acknowledge bit, and holding it low during the high period

of this clock pulse. All other devices on the bus remain idle

while the selected device waits for data to be read from or

written to it. If the R/W bit is 0, the master writes to the

slave device. If the R/W bit is 1, the master reads from the

slave device.

Data is sent over the serial bus in sequences of nine clock

pulses, 8 bits of data followed by an acknowledge bit from

the slave device. Data transitions on the data line must

occur during the low period of the clock signal and re-

main stable during the high period, because a low-to-high

transition when the clock is high may be interpreted as

a stop signal.

If the operation is a write operation, the first data byte after

the slave address is a command byte. This tells the slave

device what to expect next. It may be an instruction telling

the slave device to expect a block write, or it may simply be

a register address that tells the slave where subsequent data

is to be written.

Because data can flow in only one direction as defined by

the R/W bit, it is not possible to send a command to a slave

device during a read operation. Before doing a read oper-

ation, it may first be necessary to do a write operation to

tell the slave what type of read operation to expect and/or

the address from which data is to be read.

When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master

device releases the SDA line during the low period before

the ninth clock pulse, but the slave device does not pull

it low (called No Acknowledge). The master takes the data

line low during the low period before the 10th clock pulse,

then high during the 10th clock pulse to assert a stop

condition.

1 If it is required to perform several read or write operations in succession, the

master can send a repeat start condition instead of a stop condition to begin

a new operation.

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