ADV7192KST datasheet(25/69 Pages) AD

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ADV7192

–25–

REV. 0

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7192 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when

HSYNC is low indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the

ADV7192 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the

timing signal transitions. Mode 1 is illustrated in Figure 43 (NTSC) and Figure 44 (PAL). Figure 45 illustrates the HSYNC, BLANK and

FIELD for an odd or even ﬁeld transition relative to the pixel data.

FIELD

PIXEL

DATA

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

HSYNC

BLANK

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

Figure 45. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7192 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC

inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field.

The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines

as per CCIR-624. Mode 2 is illustrated in Figure 46 (NTSC) and Figure 47 (PAL).

522

523

524

525

123

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

VSYNC

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

HSYNC

BLANK

VSYNC

Figure 46. Timing Mode 2, NTSC

ADV7192KST Datasheet(PDF) 25 Page - Analog Devices

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