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ADV7192KST Datasheet(PDF) 27 Page - Analog Devices |
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ADV7192KST Datasheet(HTML) 27 Page - Analog Devices |
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27 / 69 page ![]() ADV7192 –27– REV. 0 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7192 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 50 (NTSC) and Figure 51 (PAL). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK HSYNC BLANK FIELD 522 523 524 525 12 34 5 67 8 9 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD HSYNC BLANK FIELD Figure 50. Timing Mode 3, NTSC 622 623 624 625 1 2 3 4 5 67 21 22 23 DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD HSYNC BLANK FIELD DISPLAY 309 310 311 312 313 314 315 316 317 318 319 334 335 336 320 DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD HSYNC BLANK FIELD DISPLAY Figure 51. Timing Mode 3, PAL |
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