ADV7192KST datasheet(33/69 Pages) AD

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ADV7192

–33–

REV. 0

MODE REGISTER 5

MR5 (MR57–MR50)

(Address (SR4–SR0) = 05H)

Mode Register 5 is a 8-bit-wide register. Figure 61 shows the

various operations under the control of Mode Register 5.

MR5 BIT DESCRIPTION

Y-Level Control (MR50)

This bit controls the component Y output level on the ADV7192

If this bit is set (0), the encoder outputs Betacam levels when

conﬁgured in PAL or NTSC mode. If this bit is set (1), the

encoder outputs SMPTE levels when conﬁgured in PAL or

NTSC mode.

UV-Levels Control (MR51–MR52)

These bits control the component U and V output levels on the

ADV7192. It is possible to have UV levels with a peak-to-peak

amplitude of either 700 mV (MR52 + MR51 = 01) or 1000 mV

(MR52 + MR51 = 10) in NTSC and PAL. It is also possible to

have default values of 934 mV for NTSC and 700 mV for PAL

(MR52 + MR51 = 00).

RGB Sync (MR53)

This bit is used to set up the RGB outputs with the sync infor-

mation encoded on all RGB outputs.

Clamp Delay (MR54–MR55)

These bits control the delay or advance of the CLAMP signal in

the front or back porch of the ADV7192. It is possible to delay or

advance the pulse by zero, one, two or three clock cycles.

Note: TTX functionality is shared with

VSO and CLAMP on Pin

62. CLAMP/

VSO Select (MR77) and TTX Input/CLAMP–VSO

Output (MR76) have to be set accordingly.

Clamp Delay Direction (MR56)

This bit controls a positive or negative delay in the CLAMP sig-

nal. If this bit is set (1), the delay is negative. If it is set (0), the

delay is positive.

Clamp Position (MR57)

This bit controls the position of the CLAMP signal. If this bit is

set (1), the CLAMP signal is located in the back porch position.

If this bit is set (0), the CLAMP signal is located in the front

porch position.

MR57

MR56

MR55

MR54

MR53

MR52

MR51

MR50

POSITIVE

NEGATIVE

MR56

CLAMP DELAY

DIRECTION

UV LEVEL CONTROL

MR52 MR51

DEFAULT LEVELS

700mV

1000mV

RESERVED

DISABLE

ENABLE

MR53

RGB SYNC

CLAMP

POSITION

FRONT PORCH

BACK PORCH

MR57

DISABLE

ENABLE

MR50

Y LEVEL

CONTROL

CLAMP DELAY

MR55 MR54

NO DELAY

PCLK

Figure 61. Mode Register 5, MR5

MR47

MR46

MR45

MR44

MR43

MR42

MR41

MR40

DISABLE

ENABLE

MR46

COLOR BAR

CONTROL

CHROMINANCE

CONTROL

ENABLE COLOR

DISABLE COLOR

MR44

GENLOCK CONTROL

MR42 MR41

DISABLE GENLOCK

ENABLE SUBCARRIER

RESET PIN

TIMING RESET

ENABLE RTC PIN

DISABLE

ENABLE

MR40

VSYNC 3H

CONTROL

BURST

CONTROL

ENABLE BURST

DISABLE BURST

MR45

ACTIVE VIDEO

LINE DURATION

720 PIXELS

710 PIXELS/702 PIXELS

MR43

INTERLACE MODE

CONTROL

INTERLACED

NONINTERLACED

MR47

Figure 60. Mode Register 4, MR4

ADV7192KST Datasheet(PDF) 33 Page - Analog Devices

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