ADV7192KST datasheet(34/69 Pages) AD

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ADV7192

–34–

REV. 0

Mode Register 6

MR6 (MR67–MR60)

(Address (SR4–SR0) = 06H)

Mode Register 6 is a 8-bit-wide register. Figure 62 shows the

various operations under the control of Mode Register 6.

MR6 BIT DESCRIPTION

Power-Up Sleep Mode Control (MR60)

After

RESET is applied this control is enabled (MR60 = 0) if

both SCRESET/RTC/TR and NTSC_PAL pins are tied high.

The ADV7192 will then power up in Sleep Mode to facilitate

low power consumption before the I

2C is initialized. When this

control is disabled (MR60 = 1, via the I

2C) Sleep Mode control

passes to Sleep Mode Control, MR27.

PPL Enable Control (MR61)

The PLL control should be enabled (MR61 = 0 ) when 4

Oversampling is enabled (MR16 = 1). When this bit is toggled,

it is also used to reset the PLL.

Reserved (MR62, MR63, MR64)

A Logical 0 must be written to these bits.

Field Counter (MR65, MR66, MR67)

These three bits are read only bits. The ﬁeld count can be read

back over the I

2C interface. In NTSC mode the ﬁeld count goes

from 0–3, in PAL Mode from 0–7.

MODE REGISTER 7

MR7 (MR77–MR70)

(Address (SR4–SR0) = 07H)

Mode Register 7 is a 8-bit-wide register. Figure 63 shows the

various operations under the control of Mode Register 7.

MR7 BIT DESCRIPTION

Color Control Enable (MR70)

This bit is used to enable control of contrast and saturation of

color. If this bit is set (1) color controls are enabled (Contrast

Control Register, U-Scale Register, V-Scale Register). If this bit

is set (0), the color control features are disabled.

Luma Saturation Control (MR71)

When this bit is set (1), the luma signal will be clipped if it reaches

a limit that corresponds to an input luma value of 255 (after

scaling by the Contrast Control Register). This prevents the

chrominance component of the composite video signal being

clipped if the amplitude of the luma is too high. When this bit is

set (0), this control is disabled.

Hue Adjust Control (MR72)

This bit is used to enable hue adjustment on the composite and

chroma output signals of the ADV7192. When this bit is set (1),

the hue of the color is adjusted by the phase offset described in

the Hue Adjust Control Register. When this bit is set (0), hue

adjustment is disabled.

Brightness Enable Control (MR73)

This bit is used to enable brightness control on the ADV7192.

The actual brightness level is programmed in the Brightness

Control Register. This value or set-up level is added to the scaled

Y data. When this bit is set (1), brightness control is enabled.

When this bit is set (0), brightness control is disabled.

Sharpness Filter Enable (MR74)

This bit is used to enable the sharpness control of the luminance

signal on the ADV7192 (Luma Filter Select has to be set to Ex-

tended, MR04–MR02 = 100). The various responses of the ﬁlter

are determined by the Sharpness Control Register. When this

bit is set (1), the luma response is altered by the amount described

in the Sharpness Control Register. When this bit is set (0), the

sharpness control is disabled. See Internal Filter Response section

for luma signal responses.

CSO_HSO Output Control (MR75)

This bit is used to determine whether

HSO or CSO TTL output

signal is output at the

CSO_HSO pin. If this bit is set (1), the

CSO TTL signal is output. If this bit is set (0), the HSO TTL

signal is output.

TTX Input/CLAMP–

VSO Output (MR76)

This bit controls whether Pin 62 is conﬁgured as an output or as

an input pin. A 1 selects Pin 62 to be an output for CLAMP or

VSO functionality. A 0 selects this pin as a TTX input pin.

MR77

MR76

MR75

MR74

MR73

MR72

MR71

MR70

DISABLE

ENABLE

MR74

SHARPNESS FILTER

ENABLE

VSO OUTPUT

CLAMP OUTPUT

MR77

CLAMP/

VSO

SELECT

DISABLE

ENABLE

MR70

COLOR CONTROL

ENABLE

CSO_HSO

OUTPUT CONTROL

HSO OUT

CSO OUT

MR75

DISABLE

ENABLE

MR72

HUE ADJUST

CONTROL

DISABLE

ENABLE

MR73

BRIGHTNESS

ENABLE CONTROL

DISABLE

ENABLE

MR71

LUMA SATURATION

CONTROL

MR76

TTX INPUT/CLAMP–

VSO

OUTPUT CONTROL

TTX INPUT

CLAMP/

VSO

OUTPUT

Figure 63. Mode Register 7, MR7

MR67

MR66

MR65

MR64

MR63

MR62

MR61

MR60

ENABLED

DISABLED

MR60

POWER-UP SLEEP

MODE CONTROL

ENABLED

DISABLED

MR61

PLL ENABLE

CONTROL

ZERO MUST

BE WRITTEN

TO THESE BITS

MR64 MR63 MR62

FIELD COUNTER

MR67 MR66 MR65

Figure 62. Mode Register 6, MR6

ADV7192KST Datasheet(PDF) 34 Page - Analog Devices

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