ADV7192KST datasheet(26/69 Pages) AD

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ADV7192

–26–

REV. 0

622

623

624

625

1234

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

VSYNC

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

320

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

DISPLAY

VSYNC

Figure 47. Timing Mode 2, PAL

Mode 2: Master Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode the ADV7192 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and

VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even

Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as

per CCIR-624. Mode 2 is illustrated in Figure 46 (NTSC) and Figure 47 (PAL). Figure 48 illustrates the HSYNC, BLANK and

VSYNC for an even-to-odd ﬁeld transition relative to the pixel data. Figure 49 illustrates the HSYNC, BLANK and VSYNC for

an odd-to-even ﬁeld transition relative to the pixel data.

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

HSYNC

VSYNC

BLANK

PIXEL

DATA

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

Figure 48. Timing Mode 2, Even-to-Odd Field Transition Master/Slave

PAL = 864

CLOCK/2

NTSC = 858

CLOCK/2

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

HSYNC

VSYNC

BLANK

PIXEL

DATA

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

Figure 49. Timing Mode 2, Odd-to-Even Field Transition Master/Slave

ADV7192KST Datasheet(PDF) 26 Page - Analog Devices

ADV7192KST Datasheet(HTML) 26 Page - Analog Devices

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