ADV7202 datasheet(3/26 Pages) AD

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REV. PrB

PRELIMINARY TECHNICAL DATA

–3–

ADV7202

5 V SPECIFICATIONS (AVDD/DVDD = 5 V 5%, V

REF = 1.235 V RSET = 1.2 k

, all specifications TMIN to TMAX unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions

POWER REQUIREMENTS

AVDD/DVDD

4.75

5.25

Normal Power Mode

IDAC

4mA

RSET = 1.2 k

Ω, RL = 300 Ω

IDSC

IADC

Sleep Mode

Current

100

µARSET = 1.2 kΩ, RL = 300 Ω

PSU Rejection Ratio

DACs

0.01

0.5

%/%

COMP = 0.1

µF

Video ADC

0.01

0.5

%/%

Aux ADC

TBD

Power-Up Time

TBD

Ref. power-up time

MPU PORT—I

2C5

SCLOCK Frequency

400

kHz

SCLOCK High Pulsewidth, t1

0.6

µs

SCLOCK Low Pulsewidth, t2

1.3

µs

Hold Time (Start Condition), t3

0.6

µs

After this period the first clock is

generated.

Setup Time (Start Condition), t4

0.6

µs

Relevant for Repeated Start Condition

Data Setup Time, t5

100

SDATA, SCLOCK Rise Time, t6

300

SDATA, SCLOCK Fall Time, t7

300

Setup Time (Stop Condition), t8

0.6

µs

MPU PORT—SPI5, 6

SCLOCK Frequency

MHz

SCLOCK High Pulsewidth, t21

TBD

kHz

SCLOCK Low Pulsewidth, t22

TBD

SI Data Setup Time, t20

TBD

SI Data Hold Time, t19

TBD

RESET Low Time

100

NOTES

1All DACs and ADCs on.

DAC is the DAC supply current.

DSC is the digital core supply current.

ADC is the ADC supply current.

5TTL input values are 0 V to 3 V, with input rise/fall times

≤3 ns, as measured between the 10% and 90% points.

Timing reference points at 50% for inputs and outputs.

6See SPI timing diagram Figures 10 and 11.

Specifications subject to change without notice.

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