TPS56921 datasheet(5/39 Pages) TI

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TPS56921

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SLVSBL4 – OCTOBER 2012

ELECTRICAL CHARACTERISTICS (continued)

TJ = –40°C to 125°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SERIAL INTERFACE (SDA AND SCL PINS)(2)(3)

LOW level input voltage, VIL

0.9

HIGH level input voltage, VIH

2.5

Hysteresis of schmitt trigger inputs, Vhys

0.16

LOW level SDA output voltage (Open drain, 3mA

0.4

sink current), VOL1

Pulse width of spikes suppressed by input filter,

tSP

SCL clock frequency, fscl

400

kHz

Hold time (repeated) START condition, tHD;STA

0.6

µs

LOW period of SCL clock, tLOW

1.3

µs

HIGH period of SCL clock, tHIGH

0.6

µs

Set-up time for a repeated START condition,

0.6

µs

tSU;STA

Data hold time, tHD;DAT

900

Data set-up time, tSU;DAT

100

Rise time (SDA or SCL), tr

20+0.1Cb(4)

300

Fall time (SDA or SCL), tf

20+0.1Cb(4)

300

Set-up time for STOP condition, tSU;STO

0.6

µs

Bus free time between STOP and START

1.3

µs

condition, tBUF

Capacitive load for each bus line, Cb

400

(2)

Refer to the I2C Timing diagram below for I2C Timing Definitions

(3)

Specified by design. Not tested in production.

(4)

Cb = capacitance of bus line in pF

I2C Timing Definitions (Reproduced from Philips I2C specification Version 1.1)

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