¦

p ´

´

Iout m ax

p m od =

2

Vout

Cout

R10 Vref

R11

Vo

Vref

×

=

-

Tss(mS) Iss( A)

C5(nF) =

Vref(V)

m

g

TPS56921

SLVSBL4 – OCTOBER 2012

www.ti.com

voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor

value can be calculated using Equation 24. For the example circuit, the soft start time is not too critical since the

output capacitor value is 2 x 100

μF which does not require much current to charge to 1.1 V. The example circuit

has the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF capacitor. In TPS56921, Iss is

2.3 µA and Vref is 0.8V.

(24)

Bootstrap Capacitor Selection

A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or

higher voltage rating.

Under Voltage Lockout Set Point

The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.

R1 is connected between VIN and the EN pin of the TPS56921 and R2 is connected between EN and GND .

The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or

brown outs when the input voltage is falling. For the example design, the minimum input voltage is 4.5 V, so the

internal UVLO thresholds are used and R1 and R2 are open. Equation 3 and Equation 4 can be used to

calculate the values for the upper and lower resistor values.

Output Voltage Feedback Resistor Selection

The resistor divider network R10 and R11 is used to set the output voltage. For the example design, 10 k

Ω was

selected for R10. Using Equation 25, R11 is calculated as 26.67 k

Ω. The nearest standard 1% resistor is 26.7

k

Ω.

(25)

Compensation Component Selection

There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal

current mode control, the design equations can be easily simplified. The power stage gain is constant at low

frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is 0

degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a

minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole

shown in Equation 26

(26)

For the TPS56921 most circuits will have relatively high amounts of slope compensation. As more slope

compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase

loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage

transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple

approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a

reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the

pspice model of (insert link here). Apply the values calculated previously to the output filter components of L1, C9

and C10. Set Rload to the appropriate value. For this design, L1 = 1.0 µH. C9 and C10 are set to 100µF each,

and the ESR is set to 3 m

Ω. The Rload resistor is 1.1 V / 4 A = 275 mΩ for approximately one half rated load.

Now the power stage characteristic can be plotted as shown in Figure 26.

28

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Product Folder Links :TPS56921