Css(nF)

Vref(V)

Tss(ms) =

Iss( A)

´

m

RT/CLK

TPS54622

Rrt

RT/CLK

mode select

TPS56921

TPS56921

SLVSBL4 – OCTOBER 2012

www.ti.com

In applications where both RT mode and CLK mode are needed, the device can be configured as shown in

Figure 20. Before the external clock is present, the device works in RT mode and the switching frequency is set

by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the

SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK

mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external

clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching

frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.

Figure 20. Works with Both RT mode and CLK mode

Slow Start (SS)

The device uses the lower voltage of the internal voltage reference or the SS pin voltage as the reference

voltage and regulates the output accordingly. A capacitor on the SS pin to ground implements a slow start time.

The device has an internal pull-up current source of 2.3

μA that charges the external slow start capacitor. The

calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 6.

The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3

μA.

(6)

When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the

device stops switching and enters low current operation. At the subsequent power up, when the shutdown

condition is removed, the device does not start switching until it has discharged its SS pin to ground ensuring

proper soft start behavior.

Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 104% of the internal

voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pull-

up resistor between the values of 10k

Ω and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a

defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The

PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V.

The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal

reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN

pin is pulled low or the SS pin is below 1.4V.

possible to “blank” the PWRGD being pulled down for some number of CLK cycles. Please refer to Explanation

of Special Codes - PWRGD Blanking Control Codes for the details.

Bootstrap Voltage (BOOT) and Low Dropout Operation

The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH

pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT

pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor

should be 0.1

μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher

is recommended because of the stable characteristics over temperature and voltage.

16

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