Top side power PGND

PVIN

VIN

PH

VOUT

Output inductor

Output capacitors

BOOT

Capacitor

Analog AGND

on internal layer

Feedback trace

VIN trace to EN

divider on internal

layer

Vias to AGND

Connect AGND

to PGND at a

single point

Set point

divider

network

RT resistor

Exposed

thermal pad

Vias to

internal

PGND

PVIN input

bypass

capacitors

VIN input

bypass

capacitor

SS

capacitor

Compen-

sation

network

EN

divider

Normally

connected

to PVIN

Vias to internal PGND

Vias to

internal

PGND

I2C I/F

Connect I2C

A0 and A1 to

AGND

PWRGD

TPS56921

SLVSBL4 – OCTOBER 2012

www.ti.com

PCB Layout Guidelines

Layout is a critical portion of good power supply design. See Figure 39 for a PCB layout example. The top layer

contains the main power traces for VIN, VOUT, and PH (switching node). Also on the top layer are connections

for the remaining pins of the TPS56921 and a large top side area filled with ground. The top layer ground area

should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter

capacitor and directly under the TPS56921. The vias under the device provide a thermal path from the exposed

thermal pad land to ground additional vias are included adjacent to the exposed thermal pad. The GND pins

should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the top

side ground area together with the internal and / or bottom side ground planes, must provide adequate heat

dissipating area. There are several signals paths that conduct fast changing currents or voltages that can interact

with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To

help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass

capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to

ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Since the PH connection is the switching

node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized

to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground

trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate

width. The small signal components should be grounded to a separate analog ground path as shown. In this

example, the analog ground (AGND) is located on an internal layer. Connect the AGND and PGND together at a

single point only. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible

to the IC and routed with minimal lengths of trace. The additional external components can be placed

approximately as shown. The VOUT pin is required to be connected to the output voltage if the serial interface is

used to set the output voltage. The A0 and A1 lines should both be connected to AGND. It may be possible to

obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good

results and is meant as a guideline.

Land pattern and stencil information is provided in the data sheet addendum.

Figure 39. PCB Layout

32

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