TPS56921

SLVSBL4 – OCTOBER 2012

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Programming the Output Voltage by Internal Regulation Mode

On the TPS56921, the serial bus is inactive until the chip is enabled and the soft start time has elapsed. Until

then, the serial bus will ignore communications and will not acknowledge. During this time, the TPS56921’s

output voltage will be determined by the external resistor divider feedback to the VSENSE pin. When SS crosses

1.2V the serial interface becomes active and the user may program VOUT by writing to the interface via SDA

mode, the VOUT pin serves as the feedback path, and the VSENSE pin voltage is ignored.

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address / direction byte followed by a single 8-bit data byte. Long-form address modes and multi-byte data

transfers are not supported in this implementation. If the TPS56921 fails to acknowledge either of these two

bytes, the master should consider the transfer to be a failure, and should issue a STOP command and try again.

The serial interface pins are composed of the SDA (Data) and SCL (Clock) pins, and the A0 and A1 pins to set

up the chip’s address. SDA and SCL are designed to be used with pullup resistors to 3.3V. A0 and A1 are

designed to be either grounded (logic LOW) or left open (logic HIGH) and should not tie to a high voltage.

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Input voltage

Logic levels for the serial interface are not fixed. For the TPS56921, a logic “0” (LOW) should be 0V and a logic

“1” (HIGH) can be any voltage between 2.5V and 3.3V. Logic HIGH is generated by external pullup resistors (see

next paragraph).

Output voltage

The serial bus has external pullup resistors, one for SCL and one for SDA. These pull up to a voltage called VDD

which must lie between 2.5V and 3.3V. The outputs are pulled down to their logic LOW levels by open-drain

outputs and pulled up to their logic HIGH levels by these external pullups. The pullups must be selected so that

the current into any chip when pulled LOW by that chip’s open drain output (=VDD/RPULLUP) is less than 3mA.

Data format

One clock pulse on the SCL clock line is generated for each bit of data to be transferred. The data on the SDA

line must be stable during the HIGH period of the SCK clock line. The HIGH or LOW state of the data line can

only change when the clock signal on the SCL line is LOW. The MSB of the address and data bytes are sent

first, that is D[6] of the address byte and the ChkSum bit for the data byte.

Start and Stop conditions

A HIGH to LOW transition on the SDA line while the SCL line is HIGH defines a START condition. A LOW to

HIGH transition on the SDA line while the SCL line is HIGH defines a STOP condition. START and STOP

conditions are always generated by the Master. The bus is considered to be BUSY after the condition. It is

considered to be free again after a minimum of 1.3µS after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. START and repeated

START are functionally identical.

Every byte of data out on the SDA line is 8 bits long. 9 clocks occur for each byte (the additional clock being for

an ACK signal put onto the bus by the TPS56921 pulling down on the bus to acknowledge receipt of the data).

Exactly two bytes should be transferred to the TPS56921 per transfer, a 7-bit address and R/W byte followed by

a data byte as shown in the following waveform:

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