PGND

VIN

V7V

EN

EN_SW

nFAULT

AGND

SW_OUT

Top Side

Power

Ground

Area

VOUT

EN_SW

nFAULT

output capacitor

output inductor

boot capacitor

Input bypass capacitor

LDO capacitor

power switch

output capacitor

Thermal VIA

Signal VIA

VOUT_BUCK

VIN

PGND

AGND

Top Side Analog

Ground Area

Bottom Side

Power

Ground Area

Thermal VIA

Signal VIA

Bottom Side

Analog

Ground Area

TPS65281, TPS65281-1

www.ti.com

SLVSBH7B – JULY 2012 – REVISED DECEMBER 2012

PCB Layout Recommendation

When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the layout diagram of Figure 36.

•

There are several signal paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power

MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect

the (-) terminal of the input capacitor as close as possible to the PGND pin. Care should be taken to minimize

the loop area formed by the bypass capacitor connections, the VIN pins, and the power ground PGND

connections.

•

Since the LX connection is the switching node, the output inductor should be located close to the LX pin, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching node,

LX, away from all sensitive small-signal nodes.

•

Connect V7V decoupling capacitor (connected close to the IC), between the V7V and the power ground

PGND pin. This capacitor carries the MOSFET drivers’ current peaks.

•

Place the output filter capacitor of the buck converter close to SW_IN pins and AGND pin. Try to minimize the

ground conductor length while maintaining adequate width.

•

The AGND pin should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching

grounding path. A ground plane is recommended connecting to this ground path.

•

The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are

sensitive to noise so the components associated to these pins should be located as close as possible to the

IC and routed with minimal lengths of trace.

•

Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of the

power components. You can connect the copper areas to PGND, AGND, VIN or any other DC rail in your

system.

•

There is no electric signal internal connected to thermal pad in the device. Nevertheless connect the exposed

pad beneath the IC to ground. Always solder the thermal pad to the board, and have as many vias as

possible on the PCB to enhance power dissipation.

Figure 36. 2-Layers PCB Layout Recommendation Diagram

Copyright © 2012, Texas Instruments Incorporated

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