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SPRUG21 Datasheet(PDF) 66 Page - Texas Instruments |
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SPRUG21 Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 214 page  TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 5-12. Megamodule Cache Configuration Registers HEX ADDRESS ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 - 0184 001F - Reserved 0184 0020 L1PCFG L1P Configuration Register 0184 0024 L1PCC L1P Cache Control Register 0184 0028 - 0184 003F - Reserved 0184 0040 L1DCFG L1D Configuration Register 0184 0044 L1DCC L1D Cache Control Register 0184 0048 - 0184 0FFF - Reserved 0184 1000 - 0184 104F - See Table 5-15, CPU Megamodule Bandwidth Management Registers 0184 1050 - 0184 3FFF - Reserved 0184 4000 L2WBAR L2 Writeback Base Address Register - for Block Writebacks 0184 4004 L2WWC L2 Writeback Word Count Register 0184 4008 - 0184 400C - Reserved 0184 4010 L2WIBAR L2 Writeback and Invalidate Base Address Register - for Block Writebacks 0184 4014 L2WIWC L2 Writeback and Invalidate Word Count Register 0184 4018 L2IBAR L2 Invalidate Base Address Register 0184 401C L2IWC L2 Invalidate Word Count Register 0184 4020 L1PIBAR L1P Invalidate Base Address Register 0184 4024 L1PIWC L1P Invalidate Word Count Register 0184 4030 L1DWIBAR L1D Writeback and Invalidate Base Address Register 0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register 0184 4038 - Reserved 0184 4040 L1DWBAR L1D Writeback Base Address Register - for Block Writebacks 0184 4044 L1DWWC L1D Writeback Word Count Register 0184 4048 L1DIBAR L1D Invalidate Base Address Register 0184 404C L1DIWC L1D Invalidate Word Count Register 0184 4050 - 0184 4FFF - Reserved 0184 5000 L2WB L2 Global Writeback Register 0184 5004 L2WBINV L2 Global Writeback and Invalidate Register 0184 5008 L2INV L2 Global Invalidate Register 0184 500C - 0184 5024 - Reserved 0184 5028 L1PINV L1P Global Invalidate Register 0184 502C - 0184 503C - Reserved 0184 5040 L1DWB L1D Global Writeback Register 0184 5044 L1DWBINV L1D Global Writeback and Invalidate Register 0184 5048 L1DINV L1D Global Invalidate Register 0184 504C - 0184 5FFF - Reserved 0184 6000 - 0184 640F - See Table 5-13, Megamodule Error Detection Correct Registers 0184 6400 - 0184 7FFF - Reserved 0184 8000 - 0184 803C - Reserved 0184 8040 MAR16 Controls the Global L2 Locations 1000 0000 - 10FF FFFF 0184 8044 MAR17 Controls the Global L2 Locations 1100 0000 - 11FF FFFF 0184 8048 MAR18 Controls the Global L2 Locations 1200 0000 - 12FF FFFF 0184 804C - 0184 81FC - Reserved 0184 8200 MAR128 Controls DDR2 CE0 Range 8000 0000 - 80FF FFFF 0184 8204 MAR129 Controls DDR2 CE0 Range 8100 0000 - 81FF FFFF 0184 8208 MAR130 Controls DDR2 CE0 Range 8200 0000 - 82FF FFFF 66 C64x+ Megamodule Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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