LPC4350_13 datasheet(95/153 Pages) NXP

95 / 153 page

LPC4350_30_20_10

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Product data sheet

Rev. 4 — 26 March 2013

95 of 153

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

[3]

Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure

the same ramp-up time for both supply voltages.

[4]

VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb =25 C.

[5]

PLL1 disabled; IRC running; CCLK = 12 MHz.

[6]

VBAT = 3.6 V.

[7]

VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz.

[8]

On pin VBAT; Tamb =25 C.

[9]

Vps corresponds to the output of the power switch (see Figure 10) which is determined by the greater of VBAT and VDD(Reg)(3V3).

[10] VDDA(3V3) = 3.3 V; Tamb =25 C.

[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[12] To VSS.

[13] The values specified are simulated and absolute values.

[14] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.

[15] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO).

[16] The parameter value specified is a simulated value excluding bond capacitance.

[17] For USB operation 3.0 V

 V

DD((IO)  3.6 V. Guaranteed by design.

[18] VDD(IO) present.

[19] Includes external resistors of 33

 1 % on D+ and D.

LPC4350 Datasheet(PDF) 95 Page - NXP Semiconductors