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HT66F20 Datasheet(PDF) 252 Page - Holtek Semiconductor Inc |
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HT66F20 Datasheet(HTML) 252 Page - Holtek Semiconductor Inc |
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252 / 298 page  Rev. 1.90 �5� �e���a�� 18� �01� Rev. 1.90 �5� �e���a�� 18� �01� HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG� BRG� BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × “×” �nknown Bit7~0 BRG7~BRG0:BaudRatevalues ByprogrammingtheBRGHbitinUCR2Registerwhichallowsselectionofthe relatedformuladescribedaboveandprogrammingtherequiredvalueintheBRG register,therequiredbaudratecanbesetup. UART Module Setup and Control Fordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ, format.Thisiscomposedofonestartbit,eightorninedatabitsandoneortwostopbits.Parity issupportedbytheUARThardwareandcanbesetuptobeeven,oddornoparity.Forthemost commondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isused asthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,along withtheparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PRENandSTOPSbitsin theUCR1register.Thebaudrateusedtotransmitandreceivedataissetupusingtheinternal8-bit baudrategenerator,whilethedataistransmittedandreceivedLSBfirst.Althoughthetransmitter andreceiveroftheUARTarefunctionallyindependent,theybothusethesamedataformatandbaud rate.Inallcasesstopbitswillbeusedfordatatransmission. • Enabling/DisablingtheUART Thebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitin theUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpins willactasnormalTXoutputpinandRXinputpinrespectively.Ifnodataisbeingtransmittedon theTXpin,thenitwilldefaulttoalogichighvalue. ClearingtheUARTENbitwilldisabletheTXandRXpinsandthesetwopinswillbeinthe stateofhighimpedance.WhentheUARTfunctionisdisabled,thebufferwillberesettoan emptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUART willalsoresettheenablecontrol,theerrorandstatusflagswithbitsTXEN,RXEN,TXBRK, RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbe set.TheremainingcontrolbitsintheUCR1,UCR2andBRGregisterswillremainunaffected. IftheUARTENbitintheUCR1registerisclearedwhiletheUARTisactive,thenallpending transmissionsandreceptionswillbeimmediatelysuspendedandtheUARTwillberesettoa conditionasdefinedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagainin thesameconfiguration. |
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