LM86 datasheet(6/33 Pages) TI1

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LM86

SNIS114E – DECEMBER 2001 – REVISED MARCH 2013

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Logic Electrical Characteristics

DIGITAL DC CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD=+3.0 to 3.6 Vdc. Boldface limits apply for TA = TJ = TMIN to

TMAX; all other limits TA= TJ=+25°C, unless otherwise noted.

Typical (1)

Limits (2)

Unit

Symbol

Parameter

Test Conditions

(Limit)

SMBData, SMBCLK INPUTS

VIN(1)

Logical “1” Input Voltage

2.1

V (min)

VIN(0)

Logical “0”Input Voltage

0.8

V (max)

VIN(HYST)

SMBData and SMBCLK Digital Input

400

Hysteresis

IIN(1)

Logical “1” Input Current

VIN = VDD

0.005

±10

µA (max)

IIN(0)

Logical “0” Input Current

VIN = 0 V

−0.005

±10

µA (max)

CIN

Input Capacitance

ALL DIGITAL OUTPUTS

IOH

High Level Output Current

VOH = VDD

µA (max)

VOL

SMBus Low Level Output Voltage

IOL = 4mA

0.4

V (max)

IOL = 6mA

0.6

(1)

Typical values are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

SMBus DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD=+3.0 Vdc to +3.6 Vdc, CL (load capacitance) on output lines = 80

pF. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

The switching characteristics of the LM86 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBData signals related to the LM86. They adhere

to but are not necessarily the SMBus bus specifications.

Typical (1)

Limits (2)

Unit

Symbol

Parameter

Test Conditions

(Limit)

fSMB

SMBus Clock Frequency

100

kHz (max)

kHz (min)

tLOW

SMBus Clock Low Time

from VIN(0)max to VIN(0)max

4.7

µs (min)

ms (max)

tHIGH

SMBus Clock High Time

from VIN(1)min to VIN(1)min

4.0

µs (min)

tR,SMB

SMBus Rise Time

(3)

µs (max)

tF,SMB

SMBus Fall Time

(4)

0.3

µs (max)

tOF

Output Fall Time

CL = 400pF,

250

ns (max)

IO = 3mA

(4)

tTIMEOUT

SMBData and SMBCLK Time Low for Reset of

ms (min)

Serial Interface (5)

ms (max)

tSU;DAT

Data In Setup Time to SMBCLK High

250

ns (min)

tHD;DAT

Data Out Stable after SMBCLK Low

300

ns (min)

900

ns (max)

tHD;STA

Start Condition SMBData Low to SMBCLK Low

100

ns (min)

(Start condition hold before the first clock

falling edge)

tSU;STO

Stop Condition SMBCLK High to SMBData

100

ns (min)

Low (Stop Condition Setup)

(1)

Typical values are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

(3)

The output rise time is measured from (VIN(0)max + 0.15V) to (VIN(1)min − 0.15V).

(4)

The output fall time is measured from (VIN(1)min - 0.15V) to (VIN(1)min + 0.15V).

(5)

Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM86's SMBus state machine,

therefore setting SMBData and SMBCLK pins to a high impedance state.

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