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LM5069 Datasheet(PDF) 4 Page - Texas Instruments |
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LM5069 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 28 page ![]() LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48V. Symbol Parameter Conditions Min. Typ. Max. Units OVLODEL OVLO delay Delay to GATE high 55 µs Delay to GATE low 11 OVLOBIAS OVLO bias current OVLO = 2.4V 1 µA Power Limit (PWR pin) PWRLIM-1 Power limit sense voltage (VIN-SENSE) SENSE-OUT = 48V, RPWR = 150 kΩ 19 25 31 mV PWRLIM-2 SENSE-OUT = 24V, RPWR = 75 kΩ 25 mV IPWR PWR pin current VPWR = 2.5V 20 µA Gate Control (GATE pin) IGATE Source current Normal Operation, GATE-OUT = 5V 10 16 22 µA Sink current UVLO < 2.5V 1.75 2 2.6 mA VIN - SENSE = 150 mV or VIN < 45 110 175 mA PORIT, VGATE = 5V VGATE Gate output voltage in normal operation GATE-OUT voltage 11.4 12 12.6 V Current Limit VCL Threshold voltage VIN-SENSE voltage 48.5 55 61.5 mV tCL Response time VIN-SENSE stepped from 0 mV to 45 µs 80 mV ISENSE SENSE input current Enabled, SENSE = OUT 23 µA Disabled, OUT = 0V 60 Circuit Breaker VCB Threshold voltage VIN - SENSE 80 105 130 mV tCB Response time VIN - SENSE stepped from 0 mV to 0.44 1.2 µs 150 mV, time to GATE low, no load Timer (TIMER pin) VTMRH Upper threshold 3.76 4 4.16 V VTMRL Lower threshold Restart cycles (LM5069-2) 1.187 1.25 1.313 V End of 8th cycle (LM5069-2) 0.3 V Re-enable Threshold (LM5069-1) 0.3 V ITIMER Insertion time current 3 5.5 8 µA Sink current, end of insertion time TIMER pin = 2V 1.0 1.5 2.0 mA Fault detection current 51 85 120 µA Fault sink current 1.25 2.5 3.75 µA DCFAULT Fault Restart Duty Cycle LM5069-2 only 0.5 % tFAULT Fault to GATE low delay TIMER pin reaches 4.0V 12 µs Power Good (PGD pin) PGDTH Threshold measured at SENSE-OUT Decreasing 0.67 1.25 1.85 V Increasing, relative to decreasing 0.95 1.25 1.55 threshold PGDVOL Output low voltage ISINK = 2 mA 60 150 mV PGDIOH Off leakage current VPGD = 80V 5 µA 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5069 |
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