Charge

Pump

GATE

VIN

OUT

SENSE

Q 1

12V

2 mA

Gate

Control

16 PA

time

Insertion

OVLO/

UVLO/

Fault /

Power Limit

Control

Current Limit

/

230 mA

Initial Hold - down

Circuit Breaker /

LM5069

SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013

www.ti.com

If the in-rush limiting condition persists such that the TIMER pin reached 4V during t2, the GATE pin is then

pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is

initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See the Fault Timer & Restart section.

If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is

pulled low by the 2 mA pull-down current to switch off Q1.

Figure 25. Gate Control

Current Limit

mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the

current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load

current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5069 resumes

Circuit Breaker

exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds

down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit

or the power limit functions. If the TIMER pin reaches 4.0V before the current limiting or power limiting condition

ceases, Q1 is switched off by the 2 mA pull-down current at the GATE pin as described in the Fault Timer &

Restart section.

Power Limit

An important feature of the LM5069 is the MOSFET power limiting. The Power Limit function can be used to

maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5069 determines

the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current

through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power

limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold,

the GATE voltage is modulated to reduce the current in Q1. While the power limiting circuit is active, the fault

timer is active as described in the Fault Timer & Restart section.

12

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