1

2

3

4

5

10

9

8

7

6

UVLO

OVLO

PWR

GND

TIMER

PGD

OUT

VIN

SENSE

GATE

LM5069

SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013

www.ti.com

CONNECTION DIAGRAM

Figure 2. Top View

10-Lead VSSOP

PIN DESCRIPTIONS

Pin #

Name

Description

Applications Information

1

SENSE

Current sense input

activates.

2

VIN

Positive supply input

A small ceramic bypass capacitor close to this pin is recommended to suppress

transients which occur when the load current is switched off.

3

UVLO

Under-voltage lockout

An external resistor divider from the system input voltage sets the under-voltage turn-

on threshold. An internal 21 µA current source provides hysteresis. The enable

threshold at the pin is 2.5V. This pin can also be used for remote shutdown control.

4

OVLO

Over-voltage lockout

An external resistor divider from the system input voltage sets the over-voltage turn-off

threshold. An internal 21 µA current source provides hysteresis. The disable threshold

at the pin is 2.5V.

5

GND

Circuit ground

6

TIMER

Timing capacitor

An external capacitor connected to this pin sets the insertion time delay and the Fault

Timeout Period. The capacitor also sets the restart timing of the LM5069-2.

7

PWR

Power limit set

An external resistor connected to this pin, in conjunction with the current sense resistor

MOSFET.

8

PGD

Power Good indicator

the PGD indicator switches low.

9

OUT

Output feedback

Connect to the output rail (external MOSFET source). Internally used to determine the

10

GATE

Gate drive output

Connect to the external MOSFET’s gate. This pin's voltage is typically 12V above the

OUT pin when enabled.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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