LM5069 datasheet(16/28 Pages) TI

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Drain Current

a) Current Limit Only

VSYS

VDS

ILIM

VGATE

VGSL

VTH

t ON

Source Voltage

Gate-

b) Power Limit and Current Limit

VDS

Drain Current

t ON

VSYS

ILIM

VGATE

VGSL

VTH

tON =

CL x VSYS

2 x PFET(LIM)

CL x PFET(LIM)

2 x ILIM

VIN

GND

PGD

OUT

GND

LM5069

SYS

R L

VIN

GND

PGD

OUT

GND

LM5069

SYS

R L

LM5069

SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013

www.ti.com

where RL is the load resistance. The Fault Timeout Period must be set longer than tON to prevent a fault

shutdown before the turn-on sequence is complete.

Figure 30. No Load Current During Turn-On

Figure 31. Load Draws Current During Turn-On

B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (PFET(LIM)) is

defined by the resistor at the PWR pin, and the current sense resistor RS. See the Power Limit Threshold

section. If the current limit threshold (ILIM) is higher than the current defined by the power limit threshold at

maximum VDS (PFET(LIM)/VSYS) the circuit operates initially at the power limit mode when the VDS of Q1 is high,

and then transitions to current limit mode as the current increases to ILIM and VDS decreases. See Figure 32ab.

Assuming the load (RL) is not connected during turn-on, the time for the output voltage to reach its final value is

approximately equal to:

For example, if VSYS = 48V, CL = 1000 µF, ILIM = 1A, and PFET(LIM) = 20W, tON calculates to ≊68 ms, and the initial

current level (IP) is approximately 0.42A. The Fault Timeout Period must be set longer than tON.

Figure 32. MOSFET Power Up Waveforms

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