AD9776-EB datasheet(28/56 Pages) AD

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AD9776/AD9778/AD9779

Rev. A | Page 28 of 56

Table 12. SPI Register Description

Address

Reg. No.

Bits

Description

Function

Default

Comm Register

SDIO bidirectional

0: use SDIO pin as input data only

1: use SDIO as both input and output data

LSB/MSB first

0: first bit of serial data is MSB of data byte

1: first bit of serial data is LSB of data byte

Software reset

Bit must be written with a 1, then 0 to soft

reset SPI register map

Power-down mode

0: all circuitry is active

1: disable all digital and analog circuitry,

only SPI port is active

Auto power-down enable

Controls auto power-down mode, see the

Power-Down and Sleep Modes section

PLL lock (read only)

0: PLL is not locked

1: PLL is locked

Digital Control Register

7:6

Filter interpolation factor

00: 1× interpolation

01: 2× interpolation

10: 4× interpolation

11: 8× interpolation

5:2

Filter modulation mode

See Table 21 for filter modes

0000

Zero stuffing

0: zero stuffing off

1: zero stuffing on

Data format

0: signed binary

1: unsigned binary

Dual/interleaved data bus mode

0: both input data ports receive data

1: Data Port 1 only receives data

Real mode

0: enable Q path for signal processing

1: disable Q path data (internal Q channel

clocks disabled, I and Q modulators

disabled)

DATACLK delay enable

See the Using Data Delay to Meet Timing

Requirements section.

Inverse sinc enable

0: inverse sinc filter disabled

1: inverse sinc filter enabled

DATACLK invert

0: output DATACLK same phase as internal

capture clock

1: output DATACLK opposite phase as

internal capture clock

TxEnable invert

Inverts the function of TxEnable Pin 39, see

the Interleaved Data Mode section

Q first

0: first byte of data is always I data at

beginning of transmit

1: first byte of data is always Q data at

beginning of transmit

Sync Control Register

7:6

Data clock delay mode

00: manual

5:4

Extra data clock divide ratio

Data clock output divider (see Table 22 for

divider ratio)

3:0

Reserved

000

7:4

Data clock delay

Sets delay of REFCLK in to DATACLK out

0000

3:1

Output sync pulse divide

Sets frequency of SYNC_O pulses

000

Sync out delay

Sync output delay, Bit 4

7:4

Sync out delay

Sync output delay, Bits<3:0>

3:1

Input sync pulse frequency

Input sync pulse frequency divider, see the

AN-822 application note

000

Sync input delay

Sync input delay, Bit 4

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