AD9776-EB datasheet(29/56 Pages) AD

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AD9776/AD9778/AD9779

Rev. A | Page 29 of 56

Address

Reg. No.

Bits

Description

Function

Default

Sync Control Register

7:4

Sync input delay

See the Multiple DAC Synchronization

section for details on using these registers

to synchronize multiple DACs

3:0

Input sync pulse timing error

tolerance

Sync receiver enable

Sync driver enable

Sync triggering edge

4:0

SYNC_I to input data sampling

clock offset

PLL Control

7:2

PLL band select

VCO frequency range vs. PLL band select

value (see Table 18)

111001

1:0

VCO AGC gain control

Lower number (low gain) is generally better

for performance

PLL enable

0: PLL off, DAC rate clock supplied by

outside source

1: PLL on, DAC rate clock synthesized

internally from external reference clock via

PLL clock multiplier

6:5

PLL VCO divide ratio

FVCO/fDAC

00 × 1

01 × 2

10 × 4

11 × 8

4:3

PLL loop divide ratio

fDAC/fREF

00 × 2

01 × 4

10 × 8

11 × 16

2:0

PLL bias setting

Always set to 010

010

7:5

PLL control voltage range

000 to 111, proportional to voltage at PLL

loop filter output, readback only

Misc Control

4:0

PLL loop bandwidth adjustment

See PLL Loop Filter Bandwidth section for

details

I DAC Control Register

7:0

I DAC gain adjustment

(7:0) LSB slice of 10-bit gain setting word

for I DAC

11111001

I DAC sleep

0: I DAC on

1: I DAC off

I DAC power-down

0: I DAC on

1: I DAC off

1:0

I DAC gain adjustment

(9:8) MSB slice of 10-bit gain setting word

for I DAC

7:0

Aux DAC1 gain adjustment

(7:0) LSB slice of 10-bit gain setting word for

Aux DAC1

00000000

Aux DAC1 sign

0: positive

1: negative

Aux DAC1 current direction

0: source

1: sink

Aux DAC1 power-down

0: Aux DAC1 on

1: Aux DAC1 off

Aux DAC1 Control

1:0

Aux DAC1 gain adjustment

(9:8) MSB slice of 10-bit gain setting word

for Aux DAC1

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