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TAS5558 Datasheet(PDF) 71 Page - Texas Instruments |
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TAS5558 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 122 page  TAS5558 www.ti.com SLES273A – APRIL 2013 – REVISED JUNE 2013 TOTAL I2C REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE (hex) BYTES SUBADDRESS 0x34 1 PWM_mux_ch1 and 2 See Table 11-21 and Table 11-22 01 0x35 1 PWM_mux_ch3 and 4 See Table 11-21 and Table 11-22 23 0x36 1 PWM_mux_ch5 and 6 See Table 11-21 and Table 11-22 45 0x37 1 PWM_mux_ch7 and 8 See Table 11-21 and Table 11-22 67 0x38 1 IC Delay Channel 0(BD See Section 11.20 80 Mode) 0x39 1 IC Delay Channel 1(BD See Section 11.20 00 Mode) 0x3A 1 IC Delay Channel 2(BD See Section 11.20 C0 Mode) 0x3B 1 IC Delay Channel 3(BD See Section 11.20 40 Mode) 0x3C 1 IC Delay Channel 4(BD See Section 11.20 A0 Mode) 0x3D 1 IC Delay Channel 5(BD See Section 11.20 20 Mode) 0x3E 1 IC Delay Channel 6(BD See Section 11.20 E0 Mode) 0x3F 1 IC Delay Channel 7(BD See Section 11.20 60 Mode) 0x40 4 Bank Switching command Set up DAP coefficients bank RESERVED register switching for banks 1, 2, and 3 41 – 80 2nd Byte – Other 00 42 – 80 6th Byte – Other 00 43 – 80 10th Byte – Other 00 Input mixer registers, 44 – 80 14th Byte – Other 00 0x41–0x48 32/reg. 8×8 input crossbar mixer setup Ch1–Ch8 45 – 80 18th Byte – Other 00 46 – 80 22nd Byte – Other 00 47 – 80 26th Byte – Other 00 48 – 80 30th Byte – Other 00 0x49 4 Bass Mixer Input mixer 1 to Ch8 mixer coefficient 0000 0000 0x4A 4 Bass Mixer Input mixer 2 to Ch8 mixer coefficient 0000 0000 0x4B 4 Bass Mixer Input mixer 7 to Ch2 mixer coefficient 0000 0000 0x4C 4 Bass Mixer Bypass Ch7 biquad 2 coefficient 0000 0000 0x4D 4 Bass Mixer Ch7 biquad 2 coefficient 0080 0000 0x4E 4 Bass Mixer Ch8 biquad 2 output to Ch1 mixer and 0000 0000 Ch2 mixer coefficient 0x4F 4 Bass Mixer Bypass Ch8 biquad 2 coefficient 0000 0000 0x50 4 Bass Mixer Ch8 biquad 2 coefficient 0080 0000 0x51–0x88 20/reg. Biquad filter register Ch1–Ch8 biquad filter coefficients All biquads = 80 2nd byte – other 00 0x89–0x90 8 Bass and treble register, Bass and treble for Ch1–Ch8 Bass and treble = 80 2nd byte – other 00 Ch1–Ch8 0x91 4 Loudness Log2 LG Loudness Log2 gain (LG) 0FC0 0000 0x92 8 Loudness Log2 LO Loudness Log2 offset (LO) 0000 0000 0x93 4 Loudness G Loudness Gain 0000 0000 0x94 4 Loudness O Loudness Offset 0000 0000 Loudness biquad coefficient b0 00FE 5045 Loudness biquad coefficient b1 0F81 AA27 0x95 20 Loudness biquad Loudness biquad coefficient b2 0000 D513 Loudness biquad coefficient a0 0000 0000 Loudness biquad coefficient a1 0FFF 2AED 0x96 4 DRC1 control Ch1–Ch7 DRC1 control Ch1–Ch7 00 00 00 00 0x97 4 DRC2 control register, Ch8 DRC2 control Ch8 00 00 00 00 Ch1–Ch7, DRC1 energy DRC1 energy 0000 883F 007F 77C0 0x98 8 Ch1–Ch7, DRC1 (1 – energy) DRC1 (1 – energy) Copyright © 2013, Texas Instruments Incorporated 71 Serial-Control I2C Register Summary Submit Documentation Feedback Product Folder Links: TAS5558 |
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