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AFE5809ZCF Datasheet(PDF) 35 Page - Texas Instruments |
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AFE5809ZCF Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 90 page ![]() AFE5809 www.ti.com SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013 word. 5. Sync Pattern: When 2[15:13]= 001, the normal ADC output is replaced by a fixed 11111110000000 word. 6. Toggle: When 2[15:13]=101, the normal ADC output is alternating between 1's and 0's. The start state of ADC word can be either 1's or 0's. 7. Custom Pattern: It can be enabled when 2[15:13]= 011;. Users can write the required VALUE into register bits <CUSTOM PATTERN> which is Register 5[13:0]. Then the device will output VALUE at its outputs, about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern will take approximately 128 x (24 SCLK clock cycles + 4 ADC clock cycles). NOTE only one of the above patterns can be active at any given instant. SYNC_PATTERN: Address: 10[8] By enabling this bit, all channels' test pattern outputs are synchronized. When 10[8] is set as 1, the ramp patterns of all 8 channels start simultaneously. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: AFE5809 |
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