AFE5809ZCF datasheet(5/90 Pages) TI

5 / 90 page

AFE5809

www.ti.com

SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013

PINOUT INFORMATION

Top View

ZCF (BGA-135)

AVDD

INP8

INP7

INP6

INP5

INP4

INP3

INP2

INP1

CM_BYP

ACT8

ACT7

ACT6

ACT5

ACT4

ACT3

ACT2

ACT1

AVSS

INM8

INM7

INM6

INM5

INM4

INM3

INM2

INM1

AVSS

AVDD

CW_IP_AMPINP

CW_IP_AMPINM

AVSS

AVDD

CW_IP_OUTM

CW_IP_OUTP

AVSS

CLKP_16X

CLKM_16X

AVSS

CLKP_1X

CLKM_1X

CW_QP_OUTM

CW_QP_OUTP

AVSS

PDN_GLOBAL

RESET

CW_QP_AMPINP

CW_QP_AMPINM

AVSS

AVDD_ADC

PDN_VCA

SCLK

AVDD

AVDD_5V

VCNTLP

VCNTLM

VHIGH

AVSS

DNC

AVDD_ADC

SDATA

CLKP_ADC

CLKM_ADC

AVDD_ADC

REFM

DNC

LDO_EN

TX_SYNC_IN

PDN_ADC

SEN

AVDD_ADC

VREF_IN

REFP

DNC

LDO_SETV

SPI_DIG_EN

DNC

SDOUT

D8P

D8M

DVDD

DVDD_LDO1

DVSS

DVDD_LDO2

DVDD

D1M

D1P

D7M

D6M

D5M

FCLKM

DVSS

DCLKM

D4M

D3M

D2M

D7P

D6P

D5P

FCLKP

DVSS

DCLKP

D4P

D3P

D2P

PIN FUNCTIONS

DESCRIPTION

NO.

NAME

B9 to B2

ACT1...ACT8

ActI've termination input pins for CH1 to 8.

A1, D8, D9,

AVDD

3.3 V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.

E8, E9, K1

AVDD_5V

5 V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.

J6, J7, K8, L3,

AVDD_ADC

1.8 V Analog power supply for ADC.

M1, M2

C1, D1 to D7,

E3 to E7, F3 to

F7, G1 to G7,

AVSS

Analog ground.

H3 to H7,J3

toJ5, K6

Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or

CLKM_ADC

through a 0.1 µF capacitor.

Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal

CLKP_ADC

directly or through a 0.1 µF capacitor.

Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the

4X, and 8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode,

CLKM_16X

this pin becomes the quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not

used. See register 0x36[11:10].

Positive input of differential CW 16X clock. In 4X, and 8X clock modes, this pin becomes the 4X, and

CLKP_16X

8X CLKP input. In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKP for the

CW mixer. Can be floated if CW mode is not used. See register 0x36[11:10].

Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer

CLKM_1X

to Figure 100 for details). In the 1X clock mode, this pin is the In-phase 1X CLKM for the CW mixer.

Can be floated if CW mode is not used.

Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the In-phase 1X CLKP for

CLKP_1X

the CW mixer. Can be floated if CW mode is not used.

Bias voltage and bypass to ground. 1µF is recommended. To suppress the ultra low frequency noise,

CM_BYP

10µF can be used.

Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be

connected between CW_IP_AMPINM and CW_IP_OUTP. This pin provides the current output for the

CW_IP_AMPINM

CW mixer. This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be

floated if not used.

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