AFE5809ZCF datasheet(43/90 Pages) TI

43 / 90 page

AFE5809

www.ti.com

SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013

Table 11. Digital Demodulator Register Map

Note: 1. When programming the SPI, 8-bit address is required. The below table and following sections only list the Add_Bit5 to

Add_Bit0. The Add_Bit7=SCID1_SEL and Add_Bit6=SCID0_SEL need to be appended as 11, 10, or 01, which determines either

SubChip1 or SubChip0 is being programmed. If SCID1_SEL,SCID0_SEL = 11, then both subchips get written with the same

register value. Please see Table 10. 2. Reserved register bits must be programmed based on their descriptions. 3. Unlisted

Add(Hex)

Add(Dec)

Default

Description

Bit[5:0]

MANUAL_TX_TRIG

00[2]

1: generate internal tx_trig (self clear, Write Only). This is an alternative

for TX_SYNC hardware pulse.

REGISTER_READOUT_E

00[1]

1:enables readout of register at SDOUT pin (Write Only)

NABLE

CHIP_ID

01[4:0]

Unique Chip ID

OUTPUT_MODE

02[15:13]

000-normal operation

011- custom pattern (set by register 05).

NOTE: LSB always comes out first no matter 0x04[4]=0 or 1

111- chipID + ramp test pattern. ChipID (5 bit) and Sub-chip information

(3 bit) are the 8 LSBs and the ramp pattern is in the rest MSBs. (0x0A[9]

= 1)

SERZ_FACTOR

03[14:13]

Serialization factor (output rate)

00-10x 01-12x 10-14x 11-16x. Note: this register is different from the ADC

SERIALIZED_DATA_RATE. The demod and ADC serilization factors

must be matched. Please see LVDS Serialization Factor.

OUTPUT_RESOLUTION

03[11:9]

Output resoluiton of the demodulator. It refers to the ADC resolution when

the demodulator is bypassed.

100-16bit(DEMOD only)

000-14bit

001-13bit

010-12bit

MSB_FIRST

04[4]

0-LSB first; 1-MSB first. This bit will not affect the test mode: customer

pattern, that is 02[15:13]=011B. Note: in the CUSTOM_PATTERN mode,

the output is always set as LSB first regardless of this bit setting.

CUSTOM_PATTERN

05[15:0]

0000

Custom data pattern for LVDS (0x02[15:13]=011)

COEFF_MEM_ADDR_WR

06[7:0]

Write address offset to coefficient memory (auto increment)

COEFF_BANK

07[111:0]

---

Writes chunks of 112 bits to the coefficient memory. This RAM does not

have default values, so it is necessary to write required values to the

RAM. It is recommended to configure the RAM before other registers.

PROFILE_MEM_ADDR_W

08[4:0]

Write address offset to profile memory (auto increment)

PROFILE_BANK

09 [63:0]

---

Writes chunks of 64 bits to the profile memory (effective 62 bits since two

LSBs are ignored). This RAM does not have default values, so it is

necessary to write required values to the RAM. It is recommended to

configure the RAM before other registers.

RESERVED

0A[15]

10[15]

Must set to 0.

MODULATE_BYPASS

0A[14]

10[14]

Arrange the demodulator output format for I/Q data. Please see Table 13.

DEC_SHIFT_SCALE

0A[13]

10[13]

0- no addtional shift applied to the decimation filter output.

1-shift the decimation filter output by 2 bits addtionally, that is apply 12dB

addtional digital gain.

RESERVED

0A[12]

10[12]

Must set to 1.

OUTPUT_CHANNEL_SEL

0A[11]

10[11]

Swap channel pairs. It is used in 4 LVDS bypass configuration to select

which of the two possible data streams to pass on. See table 13.

SIN_COS_RESET_ON_TX 0A[10]

10[10]

0-Continuous phase

_TRIG

1-Reset down convertion phase on TX_TRIG

FULL_LVDS_MODE

0A[9]

10[9]

0-Use 4 LVDS lines (1,3,5,7)

1-Use 8 LVDS lines (1-8)

Note: 4 LVDS mode valid only for decimation factors

≥4. Please see

Table 13.

RESERVED

0A[8:5]

10[8:5]

Must set to 0.

RESERVED

0A[4]

10[4]

Must set to 1.

DEC_BYPASS

0A[3]

10[3]

0-Enable decimation filter

1-Bypass decimation filter

Submit Documentation Feedback

Product Folder Links: AFE5809

AFE5809ZCF Datasheet(PDF) 43 Page - Texas Instruments

AFE5809ZCF Datasheet(HTML) 43 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL