AM3359 datasheet(105/236 Pages) TI

105 / 236 page

MPU

PLL

PER

PLL

DDR

PLL

CORE

PLL

LCD

PLL

VDDS_PLL_MPU

VDDS_PLL_CORE_LCD

VDDA1P8V_USB0

VDDS_PLL_DDR

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

www.ti.com

SPRS717F – OCTOBER 2011 – REVISED APRIL 2013

4.1.4

Digital Phase-Locked Loop Power Supply Requirements

The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor

of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display

DPLL, DDR DPLL, MPU DPLL.

Figure 4-7 illustrates the power supply connectivity implemented in the AM335x device. Table 4-1 provides

the power supply requirements for the DPLL.

Figure 4-7. DPLL Power Supply Connectivity

Table 4-1. DPLL Power Supply Requirements

SUPPLY NAME

DESCRIPTION

MIN NOM

MAX

UNITS

VDDA1P8V_USB0

Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_MPU

Supply voltage range for DPLL MPU, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_CORE_LCD

Supply voltage range for DPLL CORE and LCD, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

VDDS_PLL_DDR

Supply voltage range for DPLL DDR, Analog

1.71

1.8

1.89

Max. peak-to-peak supply noise

mV (p-p)

Power and Clocking

105

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AM3359 Datasheet(PDF) 105 Page - Texas Instruments

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