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PIC16LF1824 Datasheet(PDF) 211 Page - Microchip Technology |
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PIC16LF1824 Datasheet(HTML) 211 Page - Microchip Technology |
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211 / 440 page  2011-2013 Microchip Technology Inc. Preliminary DS40001453D-page 211 PIC16(L)F1847 24.3.7 OPERATION IN SLEEP MODE In Sleep mode, the TMRx register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMRx will continue from its previous state. 24.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 24.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 24.3.10 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function registers, APFCON0 and APFCON1. To determine which pins can be moved and what their default loca- tions are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 24-8: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 118 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 226 CCPTMRS C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 227 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 226 PR4 Timer4 Period Register 91 PR6 Timer6 Period Register 91 T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 191 TMR4 Holding Register for the 8-bit TMR4 Time Base 91 T6CON — T6OUTPS<3:0> TRM6ON T6CKPS<1:0> 191 TMR6 Holding Register for the 8-bit TMR6 Time Base 91 CCP3CON — — DC3B<1:0> CCP3M<3:0> 226 CCP4CON — — DC4B<1:0> CCP4M<3:0> 226 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 88 PR2 Timer2 Period Register 189* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 191 TMR2 Holding Register for the 8-bit TMR2 Time Base 189* TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 126 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. |
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