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EP3SL70 Datasheet(PDF) 51 Page - Altera Corporation

Part # EP3SL70
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL70 Datasheet(HTML) 51 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–41
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–42 lists the EP3SL50 row pins input timing parameters for single-ended I/O
standards.
Table 1–42. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V
LVTTL
GCLK
t
su
-0.884
-0.914
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875
ns
t
h
0.997
1.040
1.554
1.774
1.924
1.808
1.834
1.768
1.931
1.777
1.885
ns
GCLK
PLL
t
su
0.910
0.917
1.476
1.619
1.864
1.796
2.057
1.645
1.878
1.814
2.090
ns
t
h
-0.661
-0.656
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875
ns
3.3-V
LVCMOS
GCLK
t
su
-0.884
-0.914
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875
ns
t
h
0.997
1.040
1.554
1.774
1.924
1.808
1.834
1.768
1.931
1.777
1.885
ns
GCLK
PLL
t
su
0.910
0.917
1.476
1.619
1.864
1.796
2.057
1.645
1.878
1.814
2.090
ns
t
h
-0.661
-0.656
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
ns
3.0-V
LVTTL
GCLK
t
su
-0.890
-0.925
1.473
1.620
1.867
1.799
2.060
1.644
1.883
1.819
2.095
ns
t
h
1.003
1.051
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
ns
GCLK
PLL
t
su
0.904
0.906
1.557
1.773
1.921
1.805
1.831
1.769
1.926
1.772
1.880
ns
t
h
-0.655
-0.645
1.473
1.620
1.867
1.799
2.060
1.644
1.883
1.819
2.095
ns
3.0-V
LVCMOS
GCLK
t
su
-0.890
-0.925
1.482
1.633
1.882
1.814
2.075
1.653
1.893
1.829
2.105
ns
t
h
1.003
1.051
-1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890
ns
GCLK
PLL
t
su
0.904
0.906
1.548
1.760
1.906
1.790
1.816
1.760
1.916
1.762
1.870
ns
t
h
-0.655
-0.645
1.482
1.633
1.882
1.814
2.075
1.653
1.893
1.829
2.105
ns
2.5 V
GCLK
t
su
-0.878
-0.918
1.551
1.770
1.914
1.799
1.828
1.772
1.922
1.804
1.879
ns
t
h
0.991
1.044
1.554
1.698
1.914
1.845
2.111
1.718
1.928
1.862
2.141
ns
GCLK
PLL
t
su
0.916
0.913
-1.369 -1.491 -1.684 -1.629 -1.895 -1.501 -1.688 -1.635 -1.926
ns
t
h
-0.667
-0.652
1.551
1.770
1.914
1.799
1.828
1.772
1.922
1.804
1.879
ns
1.8 V
GCLK
t
su
-0.940
-0.982
1.575
1.802
1.982
1.867
1.896
1.803
1.987
1.869
1.944
ns
t
h
0.930
0.925
1.530
1.666
1.846
1.777
2.043
1.687
1.863
1.797
2.076
ns
GCLK
PLL
t
su
1.054
1.109
-1.345 -1.459 -1.616 -1.561 -1.827 -1.470 -1.623 -1.570 -1.861
ns
t
h
-0.930
-0.971
1.654
1.903
2.141
2.026
2.055
1.899
2.142
2.024
2.099
ns
1.5 V
GCLK
t
su
0.940
0.936
1.451
1.565
1.687
1.618
1.884
1.591
1.708
1.642
1.921
ns
t
h
1.044
1.098
-1.266 -1.358 -1.457 -1.402 -1.668 -1.374 -1.468 -1.415 -1.706
ns
GCLK
PLL
t
su
-0.870
-0.918
1.634
1.869
2.126
2.010
2.036
1.872
2.133
1.979
2.087
ns
t
h
1.000
0.989
1.396
1.524
1.662
1.594
1.855
1.541
1.676
1.612
1.888
ns
1.2 V
GCLK
t
su
0.984
1.045
-1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
ns
t
h
-0.821
-0.860
1.692
-1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
ns
GCLK
PLL
t
su
0.973
0.971
1.413
1.536
1.680
1.611
1.876
1.557
1.698
1.633
1.910
ns
t
h
0.935
0.987
-1.228
1.930
2.146
2.032
2.059
1.931
2.149
2.032
2.106
ns



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