EP3SL70 datasheet(18/341 Pages) ALTERA

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

Electrical Characteristics

Stratix III Device Handbook, Volume 2

Altera Corporation

Pin Capacitance

Table 1–10 lists the Stratix III device family pin capacitance.

Hot-Socketing

Table 1–11 lists the hot-socketing specifications for Stratix III devices.

Table 1–9. On-Chip Termination Variation after Power-up Calibration

(Note 1)

Symbol

Description

CCIO (V)

Commercial

Typical

Unit

dR/dV

OCT variation with voltage without re-calibration

0.029

%/mV

2.5

0.036

%/mV

1.8

0.065

%/mV

1.5

0.104

%/mV

1.2

0.177

%/mV

dR/dT

OCT variation with temperature without re-calibration

0.294

%/°C

2.5

0.301

%/°C

1.8

0.355

%/°C

1.5

0.344

%/°C

1.2

0.348

%/°C

Note to Table 1–9:

(1) Valid for V

CCIO range of ± 5% and temperature range of 0° to 85° C.

Table 1–10. Pin Capacitance for Stratix III Device Family

Symbol

Parameter

Typical

Unit

IOTB

Input capacitance on top and bottom I/O pins

IOLR

Input capacitance on left and right I/O pins

CLKTB

Input capacitance on top and bottom

non-dedicated clock input pins

4pF

CLKLR

Input capacitance on left and right

non-dedicated clock input pins

4pF

OUTFB

Input capacitance on dual-purpose clock

output and feedback pins

5pF

CLK1, CCLK3, CCLK8, and

CLK10

Input capacitance for dedicated clock input

pins

2pF

Table 1–11. Hot-Socketing Specifications for Stratix III Devices

Symbol

Parameter

Maximum

IOPIN|(DC)

DC current per I/O pin

300

A

IOPIN|(AC)

AC current per I/O pin

8 mA (1)

Note to Table 1–11:

(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin

capacitance and dv/dt is the slew rate.

EP3SL70 Datasheet(PDF) 18 Page - Altera Corporation

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