MEMORY

ARBITRATOR

8051 CPU

CORE

DMA

FLASH

SRAM

FLASH CTRL

DEBUG

INTERFACE

RESET

RESET_N

P2_4

P2_3

P2_2

P2_1

P2_0

P1_4

P1_3

P1_2

P1_1

P1_0

P1_7

P1_6

P1_5

P0_4

P0_3

P0_2

P0_1

P0_0

P0_7

P0_6

P0_5

32.768-kHz

CRYSTAL OSC

32-MHZ

CRYSTAL OSC

HIGH SPEED

RC-OSC

32-kHz

RC-OSC

CLOCK MUX and

CALIBRATION

RAM

USART 0

USART 1

TIMER 1 (16-Bit)

TIMER 3 (8-bit)

TIMER 2

(BLE LL TIMER)

TIMER 4 (8-bit)

AES

ENCRYPTION

and

DECRYPTION

WATCHDOG TIMER

IRQ

CTRL

FLASH

UNIFIED

RF_P RF_N

MODULATOR

POWER-ON RESET

BROWN OUT

RADIO

REGISTERS

POWER MGT. CONTROLLER

SLEEP TIMER

PDATA

XRAM

IRAM

SFR

XOSC_Q2

XOSC_Q1

DS ADC

AUDIO / DC

DIGITAL

ANALOG

MIXED

VDD (2 V–3.6 V)

DCOUPL

ON-CHIP VOLTAGE

REGULATOR

Link Layer Engine

I

DEMODULATOR

RECEIVE

TRANSMIT

OP-

ANALOG COMPARATOR

1-KB SRAM

FIFOCTRL

SDA

SCL

CC2541

SWRS110D – JANUARY 2012 – REVISED JUNE 2013

www.ti.com

BLOCK DIAGRAM

A block diagram of the CC2541 is shown in Figure 9. The modules can be roughly divided into one of three

categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related

modules. In the following subsections, a short description of each module is given.

Figure 9. CC2541 Block Diagram

18

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Product Folder Links: CC2541