LM27403 datasheet(30/49 Pages) TI

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OUT

overshoot

OUT

I L

)

load current, io(t)

Io1

Io2

tramp

Io2

Io1

inductor current, iL

load current, io(t)

ramp

OUT

LM27403

SNVS896 A – AUGUST 2013 – REVISED SEPTEMBER 2013

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Figure 39. Load Transient Response Representation Showing COUT Charge Surplus Or Deficit.

In a typical regulator application of 12-V input to low output voltage (say 1.2 V), it should be recognized that the

load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10% and the

large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –VOUT/L. Compared

to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of

charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess

charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level

following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb

the excess charge and rein in the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as

ΔVovershoot with step reduction in output current given by ΔIo), the output capacitance should be larger than

(12)

The ESR of a capacitor is provided in the manufacturer’s datasheet either explicitly as a specification or implicitly

in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have

significant ESR, 5 m

Ω and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some ESR and

ESL as well. Ceramic output capacitors, on the other hand, are such that the impedances related to the ESR and

ESL are small at the switching frequency, and the capacitive impedance dominates. However, depending on

package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with

applied voltage and operating temperature.

Ignoring the ESR term in Equation 11 gives a quick estimation of the minimum ceramic capacitance necessary to

meet the output ripple specification. One to four 100-µF, 6.3-V, X5R capacitors in 1206 or 1210 footprint is a

common choice. Use Equation 12 to quantify if additional capacitance is necessary to meet the load-off transient

overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale of paralleling

capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor

is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range

of interest. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low

ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk

capacitance provides low-frequency energy storage to cope with load-transient demands.

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