LM27403 datasheet(33/49 Pages) TI

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DAMP

FB2

R (C

)

R C

ESR

DAMP

L C

1 R

L C

1 R

ESR

R C

COMP

VIN

GND

Adaptive

Gate

Driver

RFB2

RC2

CC3

CC2

RFB1

RC1

CC1

VREF

PWM

Comparator

PWM Ramp

RESR

ESR

Modulator

Compensator

Power Stage

VRAMP

Error

Amp

RDAMP

Qlow-side

Qhigh-side

LM27403

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SNVS896 A – AUGUST 2013 – REVISED SEPTEMBER 2013

CONTROL LOOP COMPENSATION

The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue

dashed rings in the schematic embedded in Table 4.

The compensation network typically employed with voltage-mode control is a type-III circuit with three poles and

two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation

strategy then is to use two compensator zeros to counteract the LC double pole, one compensator pole located

to nullify the output capacitor ESR zero, with the remaining compensator pole located at one-half switching

frequency to attenuate high frequency noise. Finally, a resistor divider network to FB determines the desired

output voltage. Note that the lower feedback resistor, RFB2, has no impact on the control loop from an ac

standpoint since the FB node is the input to an error amplifier and is effectively at ac ground. Hence, the control

loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance

derating with bias voltage and temperature.

Table 4. Regulator Poles and Zeros

Power Stage Poles

Power Stage Zeros

Compensator Poles

Compensator Zeros

(1)

(2)

(1)

RESR represents the ESR of output capacitor Co.

(2)

RDAMP = D*RDS(on)high-side + (1–D)*RDS(on)low-side + Rdcr, shown as a lumped element in the schematic, represents the effective series

damping resistance.

The small-signal open-loop response of a buck regulator is the product of modulator, power train and

compensator transfer functions. The power stage transfer function can be represented as a complex pole pair

associated with the output LC filter and a zero related to the output capacitor's ESR. The dc (and low frequency)

gain of the modulator and power stage is VIN/VRAMP. Representing the gain from COMP to the average voltage at

the input of the LC filter, this is held essentially constant by the LM27403's PWM line feedforward feature at 9

V/V or 19 dB.

Complete expressions for small-signal frequency analysis are presented in Table 5. The transfer functions are

denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by

its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio

susceptibility.

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