AD6655 datasheet(34/88 Pages) AD

34 / 88 page

AD6655

Rev. A | Page 34 of

100

1000

INPUT FREQUENCY (MHz)

3.00ps

0.05ps

0.20ps

0.50ps

1.00ps

1.50ps

2.00ps

2.50ps

MEASURED

Figure 63. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD6655.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Refer to Application Note AN501 and Application Note AN756 for

more information about jitter performance as it relates to ADCs

(see www.analog.com).

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 64 through Figure 67, the power dissipated

by the AD6655 is proportional to its sample rate. In CMOS

output mode, the digital power dissipation is determined

primarily by the strength of the digital drivers and the load on

each output bit. The maximum DRVDD current (IDRVDD) can be

calculated by

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (30, in the case of the

AD6655, assuming the FD bits are inactive).

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the

Nyquist frequency of fCLK/2. In practice, the DRVDD current

is established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal. Reducing the capacitive load presented

to the output drivers can minimize digital power consumption.

The data in Figure 64 through Figure 67 was taken using the same

operating conditions as those used for the Typical Performance

Characteristics, with a 5 pF load on each output driver.

1.50

1.25

1.00

0.75

0.50

0.25

0.6

IAVDD

IDVDD

IDRVDD

0.5

0.4

0.3

0.2

0.1

100

150

125

SAMPLE RATE (MSPS)

TOTAL POWER

Figure 64. AD6655-150 Power and Current vs. Sample Rate

1.50

1.25

1.00

0.75

0.50

0.25

0.6

0.5

IAVDD

IDVDD

IDRVDD

0.4

0.3

0.2

0.1

075

125

100

SAMPLE RATE (MSPS)

TOTAL POWER

Figure 65. AD6655-125 Power and Current vs. Sample Rate

1.25

1.00

0.75

0.50

0.25

0.5

0.4

IAVDD

IDVDD

IDRVDD

0.3

0.2

0.1

075

100

SAMPLE RATE (MSPS)

TOTAL POWER

Figure 66. AD6655-105 Power and Current vs. Sample Rate

AD6655 Datasheet(PDF) 34 Page - Analog Devices

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