BF516 datasheet(31/68 Pages) AD

31 / 68 page

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

Rev. B

Page 31 of 68

January 2011

SDRAM Interface Timing

Table 28. SDRAM Interface Timing

VDDMEM

1.8V Nominal

VDDMEM

2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tSSDAT

Data Setup Before CLKOUT

1.5

tHSDAT

Data Hold After CLKOUT

1.3

0.8

Switching Characteristics

tSCLK

CLKOUT Period1

1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 11 on Page 21. Package type and reduced supply voltages affect the best-case value listed here.

12.5

tSCLKH

CLKOUT Width High

tSCLKL

CLKOUT Width Low

tDCAD

Command, Address, Data Delay After CLKOUT

2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

tHCAD

Command, Address, Data Hold After CLKOUT2

tDSDAT

Data Disable After CLKOUT

5.5

tENSDAT

Data Enable After CLKOUT

Figure 12. SDRAM Interface Timing

tSCLK

CLKOUT

tSCLKL

tSCLKH

tSSDAT

tHSDAT

tENSDAT

tDCAD

tDSDAT

tHCAD

tDCAD

tHCAD

DATA (IN)

DATA (OUT)

COMMAND,

ADDRESS

(OUT)

NOTE: COMMAND =

SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

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