BF516 datasheet(32/68 Pages) AD

32 / 68 page

Rev. B

Page 32 of 68

January 2011

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

External DMA Request Timing

Table 29 and Figure 13 describe the External DMA Request

operations.

Table 29. External DMA Request Timing1

VDDMEM/VDDEXT

1.8 V Nominal

VDDMEM/VDDEXT

2.5 V/3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing PRequirements

tDR

DMARx Asserted to CLKOUT High Setup

7.2

tDH

CLKOUT High to DMARx Deasserted Hold Time

tDMARACT

DMARx Active Pulse Width

tSCLK + 1

tDMARINACT

DMARx Inactive Pulse Width

1.75 × tSCLK

1 Because the external DMA control pins are part of the VDDEXT power domain and the CLKOUT signal is part of the VDDMEM power domain, systems in which VDDEXT and

VDDMEM are NOT equal may require level shifting logic for correct operation.

Figure 13. External DMA Request Timing

CLKOUT

tDS

DMAR0/1

(ACTIVE LOW)

DMAR0/1

(ACTIVE HIGH)

tDMARACT

tDMARINACT

tDH

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