BF516 datasheet(35/68 Pages) AD

35 / 68 page

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

Rev. B

Page 35 of 68

January 2011

RSI Controller Timing

Table 31 and Figure 19 describe RSI controller timing. Table 32

and Figure 20 describe RSI controller (high speed) timing.

Table 31. RSI Controller Timing

Parameter

Min

Max

Unit

Timing Requirements

tISU

Input Setup Time

5.6

tIH

Input Hold Time

Switching Characteristics

fPP

Clock Frequency Data Transfer Mode

MHz

fOD

Clock Frequency Identification Mode

1002

400

kHz

tWL

Clock Low Time

tWH

Clock High Time

tTLH

Clock Rise Time

tTHL

Clock Fall Time

tODLY

Output Delay Time During Data Transfer Mode

tODLY

Output Delay Time During Identification Mode

1 tPP = 1/fPP

2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

Figure 19. RSI Controller Timing

SD_CLK

INPUT

OUTPUT

tISU

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

tTHL

tTLH

tWL

tWH

tPP

tIH

tODLY

VOH (MIN)

VOL (MAX)

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