S25FS-S datasheet(111/154 Pages) SPANSION

111 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

111

Da ta

Shee t

(Prelim i nar y )

10.4.5

DDR Quad I/O Read (EDh, EEh)

The DDR Quad I/O Read command improves throughput with four I/O signals - IO0-IO3. It is similar to the

Quad I/O Read command but allows input of the address four bits on every edge of the clock. In some

applications, the reduced instruction overhead might allow for code execution (XIP) directly from S25FS-S

family devices. The Quad bit of the Configuration Register must be set (CR1V[1]=1) to enable the Quad

capability.

The instruction

 EDh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or

 EDh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or

 EEh is followed by a 4-byte address (A31-A0)

The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a

DDR fashion, with four bits at a time on each clock edge through IO0-IO3.

The maximum operating clock frequency for DDR Quad I/O Read command is 80 MHz.

For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the

IO0-IO3 signals before data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the

device’s internal circuitry enough time to access the initial address. During these latency cycles, the data

value on IO0-IO3 are “don’t care” and may be high impedance. When the Data Learning Pattern (DLP) is

enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must be left

high impedance by the host so that the memory device can drive the DLP during the dummy cycles.

The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].

Mode bits allow a series of Quad I/O DDR commands to eliminate the 8-bit instruction after the first command

sends a complementary mode bit pattern, as shown in Figure 10.38 and Figure 10.40. This feature removes

the need for the 8-bit SDR instruction sequence and dramatically reduces initial access times (improves XIP

performance). The Mode bits control the length of the next DDR Quad I/O Read operation through the

inclusion or exclusion of the first byte instruction code. If the upper nibble (IO[7:4]) and lower nibble (IO[3:0])

of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to Continuous DDR Quad I/O

Read mode and the next address can be entered (after CS# is raised high and then asserted low) without

requiring the EDh or EEh instruction, as shown in Figure 10.39 on page 112 and Figure 10.42 on page 113

thus, eliminating eight cycles from the command sequence. The following sequences will release the device

from Continuous DDR Quad I/O Read mode; after which, the device can accept standard SPI commands:

1. During the DDR Quad I/O Read Command Sequence, if the Mode bits are not complementary the

next time CS# is raised high and then asserted low the device will be released from DDR Quad I/O

Read mode.

2. Send the Mode Reset command.

The address can start at any byte location of the memory array. The address is automatically incremented to

the next higher address in sequential order after each byte of data is shifted out. The entire memory can

therefore be read out with one single read instruction and address 000000h provided. When the highest

address is reached, the address counter will wrap around and roll back to 000000h, allowing the read

sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

Note that the memory devices may drive the IOs with a preamble prior to the first data value. The preamble is

a Data Learning Pattern (DLP) that is used by the host controller to optimize data capture at higher

frequencies. The preamble drives the IO bus for the four clock cycles immediately before data is output. The

host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the preamble.

The preamble is intended to give the host controller an indication about the round trip time from when the host

drives a clock edge to when the corresponding data value returns from the memory device. The host

controller will skew the data capture point during the preamble period to optimize timing margins and then use

the same skew time to capture the data during the rest of the read operation. The optimized capture point will

be determined during the preamble period of every read operation. This optimization strategy is intended to

compensate for both the PVT (process, voltage, temperature) of both the memory device and the host

controller as well as any system level delays caused by flight time on the PCB.

Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP

of 34h. The DLP 34h (or 00110100) will be driven on each of the active outputs (i.e. all four SIOs). This

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