S25FS-S datasheet(118/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

10.6.3

Bulk Erase (BE 60h or C7h)

The Bulk Erase (BE) command sets all bits to 1 (all bytes are FFh) inside the entire flash memory array.

Before the BE command can be accepted by the device, a Write Enable (WREN) command must be issued

and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any

write operations.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on

SI. This will initiate the erase cycle, which involves the pre-programming and erase of the entire flash memory

array. If CS# is not driven high after the last bit of instruction, the BE operation will not be executed.

As soon as CS# is driven into the logic high state, the erase cycle will be initiated. With the erase cycle in

progress, the user can read the value of the Write-In Progress (WIP) bit to determine when the operation has

been completed. The WIP bit will indicate a 1 when the erase cycle is in progress and a 0 when the erase

cycle has been completed.

A BE command can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0s. If the BP

bits are not 0, the BE command is not executed and E_ERR is not set. The BE command will skip any sectors

protected by the DYB or PPB and the E_ERR status will not be set.

Figure 10.49 Bulk Erase Command Sequence

This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3, two clock

cycles per byte.

Figure 10.50 Bulk Erase Command Sequence QPI Mode

CS#

SCK

Phase

Instruction

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruction

S25FS-S Datasheet(PDF) 118 Page - SPANSION