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DM383 Datasheet(PDF) 110 Page - Texas Instruments

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Part # DM383
Description  DM383 DaVinc Digital Media Processor
PDF  267 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM383 Datasheet(HTML) 110 Page - Texas Instruments

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DM383
SPRS870B – APRIL 2013 – REVISED DECEMBER 2013
www.ti.com
4.2.5
SPI Boot
Table 4-6 lists the device pins that are configured by the ROM for the SPI boot mode.
Table 4-6. Pins Used in SPI Bootmode
SIGNAL NAME
PIN NO.
TYPE
SPI[0]_SCS[0]
G29
I/O
SPI[0]_D[0] (MISO)
J28
I/O
SPI[0]_D[1] (MOSI)
J27
I/O
SPI[0]_SCLK
N24
I/O
4.2.6
UART Bootmode
Table 4-7 lists the device pins that are configured by the ROM for the UART boot mode.
Table 4-7. Pins Used in UART Bootmode
SIGNAL NAME
PIN NO.
TYPE
UART0_RXD
J26
I
UART0_TXD
E28
O
4.3
Pin Multiplexing Control
Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –
PINCNTL270 registers in the Control Module.
Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output
data values. Table 4-8 shows the peripheral pin functions associated with each MUXMODE setting for all
multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in
which case the pin's I/O buffer is 3-stated.
In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of
the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated
peripheral when its peripheral function is not selected to control any output pin. For more details on the
De-Selected Input State (DSIS), see the columns of each Terminal Functions table (Section 3.3, Terminal
Functions).
Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin
functions are called Multimuxed and may have different Switching Characteristics and Timing
Requirements for each device pin option.
For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers
breakout, see Figure 4-1 and Table 4-8.
Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout
31
24
23
20
19
18
17
16
RESERVED
RESERVED
RSV
RSV
PLLTY
PLLU
PESE
DEN
L
R - 0000 0000
R - 0000
R/W
15
8
7
0
RESERVED
MUXMODE[7:0]
R - 0000 0000
R/W - 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
110
Device Configurations
Copyright © 2013, Texas Instruments Incorporated
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