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MPQ4462 Datasheet(PDF) 17 Page - Monolithic Power Systems |
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MPQ4462 Datasheet(HTML) 17 Page - Monolithic Power Systems |
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17 / 20 page ![]() MPQ4462 – 3.5A, 4MHz, 36V, STEP-DOWN CONVERTER, AEC-Q100 QUALIFIED MPQ4462 Rev. 1.11 www.MonolithicPower.com 17 7/17/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. PCB LAYOUT GUIDE PCB layout is very important for system stability. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 6 for reference. 1) Keep the path of switching current short and minimize the loop area formed by input capacitor, high-side MOSFET and external switching diode. Place ceramic bypass capacitors close to the VIN Pin. 2) Make all feedback connections short and direct. Try to run the feedback trace as far from the inductor and noisy power traces as possible. If possible run the feedback trace on the opposite PCB side to the inductor with a ground plane separating the two. 3) Place the feedback resistors and compensation components as close to the chip as possible. Do not place the compensation components close to or under high dv/dt SW node, or inside the high di/dt power loop. If you have to do so, the proper ground plane must be in place to isolate those. 4) Connect VIN, SW, and especially GND respectively to large copper areas to cool the chip to improve thermal performance and long-term reliability. To help to improve the thermal conduction at high frequencies, add a grid of thermal vias under the exposed pad. Use small vias (15mil barrel diameter) so that the hole fills up during the plating process and improve thermal conduction. Larger vias can cause solder wicking during the reflow process. A pitch (distance between the centers) of 40mil between thermal vias is typical. 5) Place the input decoupling capacitor, catch diode and the MPQ4462 (VIN, SW and PGND) as close as possible, with traces that are very short and fairly wide. This can help to greatly reduce the voltage spike on SW node, and lower the EMI noise level as well. 6) Please refer to the layout example on EVQ4460 datasheet. C1 C3 R2 R1 L1 C4 C2 D1 VOUT VIN VIN EN FREQ GND BST SW FB COMP EN R5 R6 R3 R4 Figure 6: Typical Application Circuit |
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