AM79C974 datasheet(149/153 Pages) AMD

149 / 153 page

AMD

A M E N D M E N T

Am79C974

DMA Registers

The following is a summary of the DMA register set or

the DMA Channel Context Block (DMA CCB). These

registers control the specifics for DMA operations such

as transfer length and scatter-gather options. The three

read-only working counter registers allow the system

software and driver to monitor the DMA transaction.

Each register address is represented by the PCI Con-

figuration Base Address (B) and its corresponding offset

value. The Base address for the Am79C974 is stored at

Table 6. The DMA Registers

Addr (Hex)

Type

CMD

(B)+40

Command

(bits 31:8 reserved, bits 7:0 used)

R/W

STC

(B)+44

Starting Transfer Count

(bits 31:24 reserved, bits 23:0 used)

R/W

SPA

(B)+48

Starting Physical Address

(bits 31:0 used)

R/W

WBC

(B)+4C

Working Byte Counter

WAC

(B)+50

Working Address Counter

(bits 31:0 used)

STATUS

(B)+54

Status Register

(bits 31:8 reserved, bits 7:0 used)

SMDLA

(B)+58

Starting Memory Descriptor List (MDL) Address

R/W

WMAC

(B)+5C

Working MDL Counter

Command Register (CMD)

The upper 3 bytes of Command register are reserved,

the remaining (LSB) byte is defined as follows:

Address (B)+40h, LSB

READ/WRITE

DIR

INTE_D

INTE_P

MDL

Reserved Reserved

CMD1

CMD0

DIR:

Data transfer direction bit.

INTE_D:

DMA transfer active interrupt bit.

INTE_P:

Page transfer active interrupt bit.

MDL:

Memory Descriptor List (MDL) SPA enable bit.

RESERVED:

Reserved for future expansion. The zero value must be

written in these bits.

CMD1-0:

These two bits are encoded to represent four com-

mands: IDLE, BLAST, START, and ABORT.

CMD1

CMD0

Command

Description

IDLE

Resets the DMA block to the IDLE state. Stops any current transfer. Does not

affect status bits or cause an interrupt.

BLAST

Empties all data bytes in DMA FIFO to memory during a DMA

write operation. Upon completion, the ‘BCMPLT’ bit will be set

in the DMA Status register. This command should not be used

during a DMA read operation.

ABORT

Terminates the current DMA transfer. The DMA engine

should be restored to the ‘IDLE’ state following execution of

this command.

Note: This is only valid after a ‘START’ command is issued.

START

Initiates a new DMA transfer. These bits must remain set

throughout the DMA operation until the ‘DONE’ bit in the DMA

Status Register is set.

Note: This command should be issued only after all other

control bits have been initialized.

AM79C974 Datasheet(PDF) 149 Page - Advanced Micro Devices

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