Timer

The 6-bit programmable timer can select PH3/PH9/PH15/FREQ (timer 2 can also select PH5/PH7/PH11/

PH13 by TM2X instruction) as the clock source. When it underflows, the HALT release signal is generated.

Predivider

The predivider is a 15-stage counter that uses PH0 as the clock source. The output of T-F/F is changed when

the input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed, or

power-on or external reset is used. When PH14 is changed from H to L, the HALT release signal is generated.

Alarm/frequency/melody

There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output

from BZ/BZB.

The frequency counter can use software to select 1/2 duty, 1/3 duty or 1/4 duty drive mode.

Freq.

1/2 Duty Frequency

1/3 Duty Frequency

1/4 Duty Frequency

INT function

The INT pin can be selected by mask option as pull-high/pull-low or none, and rising edge/falling edge trigger.

Watchdog timer

The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is

8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The

watchdog enable flag will be disabled by power-on reset or reset-pin reset condition, but cannot be disabled

by watchdog reset itself.

HALT function

The HALT instruction will disable all clocks except the predivider, timer, frequency counter, PWM, EL-light

generator and chattering clock to minimize the operating current.

STOP function

The STOP instruction will disable all clocks to minimize the standby current, so only two external factors (INT,

IOA/IOC/S port, keyscan) can release the STOP condition.

Instruction Table (Total 150 instructions)

Instruction

Machine Code

Function

Flag/Remark

NOP

0000 0000 0000 0000

No Operation

LCT Lz, Ry

0000 001Z ZZZZ YYYY

Lz

{ 7SEG

Ry}

LCB Lz, Ry

0000 010Z ZZZZ YYYY

Lz

{ 7SEG

Ry}

LCP Lz, Ry

0000 011Z ZZZZ YYYY

Lz

Ry , AC

LCD Lz, @HL

0000 100Z ZZZZ 0000

Lz

T@HL

LCT Lz, @HL

0000 100Z ZZZZ Z-01

Lz {7SEG @HL

Preliminary

10

Ver. 0.0