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APU429 Datasheet(PDF) 17 Page - Aplus Intergrated Circuits

Part # APU429
Description  4-Bit Micro-controller With LCD Driver
PDF  18 Pages
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Manufacturer  APLUS [Aplus Intergrated Circuits]
Direct Link  http://www.aplusinc.com.tw
Logo APLUS - Aplus Intergrated Circuits

APU429 Datasheet(HTML) 17 Page - Aplus Intergrated Circuits

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Symbol description
AC
: Accumulator
D
: Immediate Date
ACn
: Accumulator Bit N
PC
: Program Counter
X
: Address
CF
: Carry Flag
Rx
: Memory of Address X
ZERO
: Zero Flag
Rxn
: Memory Bit N of Address X
WDF
: Watchdog Timer Enable Flag
Ry
: Memory of Working Register Y
HL
: Index Register
BCF
: Backup Flag
BCLK
: System clock stops only in STOP condition
@HL
: Addres s of Index
IEFn
: Interrupt Enable Flag
HRFn
: HALT Release Flag
SRFn
: STOP Release Enable Flag
HEFn
: HALT Release Enable Flag
SCFn
: Start Condition Flag
Cfq
: Clock Source of Frequency Generator
Cch
: Clock Source of Chattering Detector
Ctm
: Clock Source of Timer
TMR
: Timer Overflow Release Flag
Fout
: RFC Frequency
( )
: Content of Register
PDV
: Predivider
SEFn
: Switch Enable Flag
Lz
: LCD Latch
FREQ
: Frequency Generator Setting Value
T@HL
: Address of Index ROM
ADF
: ADC Flag
CSF
: Clock Source Flag
DAC
: Digital-to-Analog Converter Output Signal
@L
: Low Address of Index
@H
: High Address of Index
RFOVF
: RFC Overflow Flag
H(T@HL) : High Nibble of Index ROM
L(T@HL) : Low Nibble of Index ROM
Appendix (Important Issue for
APU429/428)
Chip’s internal vlotage V.S. power mode and external connection
AG
LI
EXT-V
Note
VDD1
Vsupply
1/2 × Vsupply
1/2 × Vsupply
VDD2
2 × VDD1
Vsupply
Vsupply
VDD3
3 × VDD1
3/2 × Vsupply
3/2 × Vsupply
*1
VDD4
4 × VDD1
2 × Vsupply
2 × Vsupply
*2
BCF=0
BCF=1
BAK
VDD1
VDD1
VDD2
VDD2
*3
Note: *1: VDD3 is only used for LCD operating in 1/3 bias and 1/4 bias. If 1/2 bias chosen, VDD3 need be
connected to VDD2 (VDD3 is equal to VDD2).
*2: VDD4 is only used for LCD operating in 1/4 bias. If 1/3 bias chosen, VDD4 need be connected to VDD3
(VDD4 is equal to VDD3). If 1/2 bias chosen, VDD4 need be connected to VDD2 (VDD4 is equal to VDD2).
*3: BAK is defined as chip’s internal power supply node, which is used only for internal logic circuitry.
A. Whatever the power mode used, all external VDD# pins must connect a capacitor (0.05 F or 0.1 F) to
GND for decoupling power noise using.
B. All VDD# pins other than Vsupply are from voltage charge pump, i.e. If no clock, then VDD# pins can
not supply out.
C. Vsupply is the power supply for Chip and depends on the power mode used, all the input and output
pins voltage range follow the Vsupply.
The capacitor connected between CUP2 and CUP3 is only when
APU429 operating in 1/4 bias.
Some notes for BCF flag
BCF is always set to High automatically after Power on, Reset and STOP mode.
A. For power saving use, BCF may be set to Low which can reduce chip’s current consumption.
Preliminary
17
Ver. 0.0



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