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EP2C8A Datasheet(PDF) 31 Page - Altera Corporation |
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EP2C8A Datasheet(HTML) 31 Page - Altera Corporation |
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31 / 168 page  Altera Corporation 2–19 February 2007 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture Figure 2–12. EP2C15 & Larger PLL, CLK[], DPCLK[] & Clock Control Block Locations Notes to Figure 2–12: (1) There are four clock control blocks on each side. (2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. The other CDPCLK pins can be used as general-purpose I/O pins. PLL 4 PLL 3 PLL 2 CLK[7..4] DPCLK7 CDPCLK5 CDPCLK4 DPCLK6 CLK[3..0] DPCLK0 CDPCLK0 CDPCLK1 DPCLK1 CDPCLK7 DPCLK[9..8] DPCLK[11..10] CLK[11..8] GCLK[15..0] GCLK[15..0] PLL 1 CDPCLK6 CDPCLK2 DPCLK[5..4] DPCLK[3..2] CLK[15..12] CDPCLK3 Clock Control Block (1) Clock Control Block (1) 16 16 16 16 22 4 4 4 4 4 2 2 4 (2) (2) (2) (2) 4 4 3 3 3 3 |
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