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TSL2583 Datasheet(PDF) 11 Page - ams AG |
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TSL2583 Datasheet(HTML) 11 Page - ams AG |
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11 / 33 page ![]() TSL2581, TSL2583 LIGHT-TO-DIGITAL CONVERTER TAOS134A − JULY 2012 10 r r Copyright E 2012, TAOS Inc. The LUMENOLOGY r Company www.taosinc.com Command Register The command register specifies the address of the target register for subsequent read and write operations and contains eight bits as described in Table 3. The command register defaults to 00h at power on. Table 3. Command Register 6 75 4 ADDRESS 2 31 0 CMD TRANSACTION Reset 00h Bit : FIELD BIT DESCRIPTION CMD 7 Select command register. Must write as 1 when addressing COMMAND register. Select type of transaction to follow in subsequent data transfers: FIELD VALUE DESCRIPTION 00 Repeated byte protocol transaction TRANSACTION 6:5 01 Auto-increment protocol transaction TRANSACTION 6:5 10 Reserved — Do not use 11 Special function — See description below Transaction type 00 will repeatedly read the same register with each data access. Transaction type 01 will provide an auto−increment function to read successive register bytes. Address field/special function field. Depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. The field values listed below apply only to special function commands: FIELD VALUE DESCRIPTION 00000 Reserved. Write as 0000b. ADDRESS 40 00001 Clear any pending interrupt and is a write−once−to−clear bit ADDRESS 4:0 00010 When the Timing Register is set to 00h, a SendByte command with the ADDRESS field set to 0010b will stop a manual integration. The actual length of the integration cycle may be read in the MANUAL INTEGRATION TIMER Register. 00011 When the Timing Register is set to 00h, a SendByte command with the ADDRESS field set to 0011b will start a manual integration. The actual length of the integration cycle may be read in the MANUAL INTEGRATION TIMER Register. x11xx Reserved. Write as 11xxb. NOTE: An I2C block transaction will continue until the Master sends a stop condition. Only the Send Byte Protocol should be used when clearing interrupts. |
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