TSL2581, TSL2583

LIGHT-TO-DIGITAL CONVERTER

TAOS134A − JULY 2012

11

The LUMENOLOGY

r Company

r

r

Copyright

E 2012, TAOS Inc.

www.taosinc.com

Control Register (00h)

The CONTROL register primarily used to power the TSL258x device up and down as shown in Table 4.

Table 4. Control Register

6

75

4

POWER

2

31

0

Reserved

Resv

ADC_VALID

Reserved

ADC_EN

ADC_INTR

Address

00h

Reset

00h

Bit :

FIELD

BIT

DESCRIPTION

Reserved

7:6

Reserved. Write as 0.

ADC_INTR

5

ADC Interrupt. Read only. Indicates that the device is asserting an interrupt.

ADC_VALID

4

ADC Valid. Read only. Indicates that the ADC channel has completed an integration cycle.

Reserved

3:2

Reserved. Write as 0.

ADC_EN

1

ADC Enable. This field enables the two ADC channels to begin integration. Writing a 1 activates the ADC

channels, and writing a 0 disables the ADCs.

POWER

0

Power On. Writing a 1 powers on the device, and writing a 0 turns it off.

NOTE: ADC_EN and POWER must be asserted before the ADC changes will operate correctly. After POWER is asserted, a 2-ms delay is

required before asserting ADC_EN.

NOTE: The TSL258x device registers should be configured before ADC_EN is asserted.

Timing Register (01h)

The TIMING register controls the internal integration time of the ADC channels in 2.7-ms increments. The

TIMING register defaults to 00h at power on.

Table 5. Timing Register

6

75

4

2

31

0

ATIME

Address

01h

Reset

00h

Bit :

FIELD

BIT

DESCRIPTION

Integration Cycles. Specifies the integration time in 2.7-ms intervals. Time is expressed as a 2’s

complement number. So, to quickly work out the correct value to write: (1) determine the number of

2.7-ms intervals required, and (2) then take the 2’s complement. For example, for a 1

0xFF should be written. For 2

is 688.5 ms (00000001b).

Writing a 0x00 to this register is a special case and indicates manual timing mode. See CONTROL and

MANUAL INTEGRATION TIMER Registers for other device options related to manual integration.

INTEG_CYCLES

TIME

VALUE

ATIME

7:0

−

Manual integration

00000000

ATIME

7:0

1

2.7 ms

11111111

2

5.4 ms

11111110

19

51.3 ms

11101101

37

99.9 ms

11011011

74

199.8 ms

10110110

148

399.6 ms

01101100

255

688.5 ms

00000001

NOTE: The Send Byte protocol cannot be used when ATIME is greater than 127 (for example ATIME[7] = 1) since the upper bit is set aside for

write transactions in the COMMAND register.